Multiprocessor communication using reduced addressing lines
AssigneeCompaq Computer Corporation
InventorsJavier F. Izquierdo, John A. Landry
Life of this patent
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Abstract
A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.
Claims38
A method for transmitting signals using a reduced number of signal lines, the method comprising:
- transmitting a first signal over a first transmission path;
- encoding the first signal into an abbreviated signal representing the first signal;
- transmitting the abbreviated signal over a second transmission path having reduced transmission capacity;
- and
- decoding the abbreviated signal into a second signal matching the first signal.
A method for transmitting signals between multiple circuit boards using a reduced number of signals, the method comprising:
- receiving a first set of signals on a first circuit board;
- encoding the first set of signals into a second set of signals having a reduced number of signals, the second set of signals representing the first set of signals;
- transmitting the second set of signals to a second circuit board;
- and
- decoding the second set of signals into a third set of signals matching the first set of signals.
A computer communications system for transmitting signals among system devices using a reduced number of signal lines, the computer communications system comprising:
- an originating device producing a first set of signals;
- an encoding device coupled to the originating device for encoding the first set of signals into a second set of signals representing the first set of signals and having an abbreviated form;
- a decoding device coupled to the encoding device for decoding the second set of signals into a third set of signals matching the first set of signals;
- and
- a target device coupled to the decoding device for receiving the third set of signals.
A computer system for transmitting signals among multiple circuit boards using a reduced signal path, the computer system comprising:
- a first circuit board having a first transmission path;
- a second circuit board having a second transmission path;
- an originating device located on the first circuit board for transmitting a first signal on the first transmission path;
- an encoding device coupled to the first transmission path for encoding the first signal to an abbreviated signal representing the first signal;
- a connecting transmission path coupled to the encoding device, for transmitting the abbreviated signal, the connecting transmission path having reduced transmission capacity;
- a decoding device coupled to the connecting transmission path for decoding the abbreviated signal to a second signal matching the first signal;
- and
- a target device located on the second circuit board for receiving the second signal on the second transmission path.
Dependencies are inferred from the claim text.