Method and arrangement for passing data between a reference chip and an external bus

An arrangement for passing data between a first bus on a reference chip and an external bus without using a bridge clocking protocol, the arrangment comprising:

• two-way buffer means for buffering data between the external bus and the first bus;
• means for determining an initiating bus of the two-way buffer means, wherein the initiating bus is the first bus on the reference chip if the data passing across the two-way buffer means is sourced by a device on the reference chip, and the initiating bus is the external bus if the data passing across the two-way buffer means is sourced by a device external to the reference chip;
• and
• means, responsive to the determination means, for controlling the two-way buffer means to asynchronously copy data through the two-way buffer means from the initiating bus to the other one of the external bus and the first bus, wherein data is passed automatically in response to its presence at the buffer means without any clock cycle delays.

An arrangement for passing data between a first bus on a reference chip and an external bus without using a bridge clocking protocol, the arrangement comprising:

• a two-way buffer arrangement between the external bus and the first bus;
• a logic circuit adapted to determine an initiating bus of the two-way buffer arrangement, wherein the initiating bus is the first bus on the reference chip if the data passing across the buffer arrangement is sourced by a device on the reference chip, and the initiating bus is the external bus if the data passing across the buffer arrangement is sourced by a device external to the reference chip;
• and
• wherein the logic circuit is further adapted to respond to the determination by controlling the two-way buffer arrangement to asynchronously copy data through the two-way buffer arrangement from the initiating bus to the other one of the external bus and the first bus, wherein data is passed automatically in response to its presence at the buffer arrangement without any clock cycle delays.