Upstream situated apparatus and method within a computer system for controlling data flow to a downstream situated input/output unit

A computer controlled graphics display system comprising an apparatus for controlling flow of input/output data, said apparatus comprising:

• a) a processor for generating stores that include input/output data, said processor comprising a processor buffer;
• b) a graphics unit coupled to receive said input/output data from said processor for processing said input/output data to render image data, said graphics unit comprising an internal input/output buffer;
• and
• c) a communication bridge coupled between said processor and said graphics unit for transmitting input/output data from said processor to said graphics unit, said communication bridge comprising a plurality of coupled communication devices wherein individual communication devices contain buffers and wherein a first upstream communication device comprises control circuitry for controlling flow of said input/output data from said processor to said graphics unit, said control circuitry comprising:
• a counter circuit maintaining a count value, said count value updated upon input/output data sent to said graphics unit from said processor and said count value updated upon credit signals received by said first upstream communication device from said graphics unit, said count value indicative of available buffer space within said internal input/output buffer for accommodating additional input/output data to be transmitted from said processor to said input/output unit, said communication bridge communicating said credit signals;
• and
• processor control circuitry for regulating flow of input/output data from said processor to said graphics unit based on said count value of said counter circuit.

A method for controlling flow of input/output data between a processor and an input/output unit coupled together via a communication bridge, said method comprising the steps of:

• a) within a first upstream communication device of said communication bridge, detecting input/output data transmitted from said processor to an input/output buffer of said input/output unit and responsive thereto generating a first count update signal;
• b) within said first upstream communication device of said communication bridge, detecting credit signals transmitted from said input/output unit to said first upstream communication device and responsive thereto generating a second count update signal;
• c) maintaining a count value based on said first count update signal and said second count update signal;
• and
• d) asserting signals to said processor to control flow of said input/output data to said input/output unit based on said count value wherein said step d) comprises the steps of:
• d1) asserting a bus line signal to said processor causing said processor to temporarily suspend transmitting said input/output data, said step d1) invoked provided said count value reaches a predetermined value;
• d2) initiating counting of a predetermined time period provided said count value reaches a predetermined value;
• d3) resetting said counting of said time period and deasserting said bus line signal provided a credit signal of said credits signals is received by said first upstream communication device from said input/output unit;
• and
• d4) generating a processor interrupt signal causing said processor to temporarily suspend generating said input/output data provided said time period expires.