DMA with dynamically assigned channels, flexible block boundary notification and recording, type code checking and updating, commands, and status reporting

An apparatus comprising a DMA controller and a memory, the DMA controller having registers including a list address register, the list address register adapted to store the memory location of a list entry, wherein the list entry is structured to include an address field, a length field and a status field, wherein for at least some of the values of the status field, the address field indicates a location of an associated buffer in the memory, wherein the DMA controller is adapted to modify the contents of the status field after the associated buffer is processed, the DMA controller further adapted to check the value of the status field before operating on an associated buffer.

An apparatus comprising a DMA controller and a memory, the DMA controller having registers including a list address register, the list address register adapted to store the memory location of a list entry, wherein the list entry is structured to include an address field, a length field and a status field, wherein for at least some of the values of the status field, the address field indicates a location of an associated buffer in the memory, wherein the DMA controller is adapted to modify the contents of the status field after the associated buffer is processed, the DMA controller further adapted to check the value of the status field before operating on an associated buffer, wherein at least some values of the status field indicate that the buffer should not be operated on, wherein said at least some values include bytes constructed of all logical "ones" and bytes constructed of all logical "zeros."

An apparatus comprising a DMA controller and a memory, the DMA controller having registers including a list address register, the memory including list entries arranged to include an address field, a length field and a status field, the list address register adapted to store a memory address pointing to one of the list entries, wherein for at least some of the values of the status field, the address field indicates the location of an associated buffer in the memory, wherein when more than one of such buffers contain data for a block of data to be sent to a peripheral device, the DMA device is adapted to transfer the data by processing a number of buffer areas associated with a number of list entries, wherein the status field of the list entry associated with the last buffer in the block contains an indication that notification of the end of the block is to be sent to the peripheral device.

An apparatus comprising a DMA controller and a memory, the DMA controller having registers including a list address register, the memory including list entries arranged to include an address field, a length field and a status field, the list address register adapted to store a memory address pointing to one of the list entries, wherein for at least some of the values of the status field, the address field indicates a location of an associated buffer in the memory, wherein the DMA controller is adapted to store a block of data from a peripheral device into more than one buffer such that, as long as no terminate signal is received, each buffer is filled with data, but when a terminate signal is received from the peripheral device indicating the end of a block, only the remaining data for that block is stored in the buffer, and if more data is being sent a new buffer is used.