US 6,154,715 AGranted

Integrated circuit tester with real time branching

AssigneeCredence Systems Corporation

InventorsBryan J. Dinteman, Daniel J. Bedell

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Abstract

An integrated circuit (IC) tester includes a set of digital and analog channels, each of which may be programmed to carry out a sequence of test activities at pins of an IC under test. The channels are interconnected by a trigger bus, and each channel may be programmed to respond to a detected event during a test by transmitting a particular trigger code to every other channel via the trigger bus. Each channel may be also programmed to respond to a particular trigger code arriving on the trigger bus by branching its sequence of test activities. Thus any channel detecting an event during a test can signal all other channels to immediately terminate a current sequence of test activities and branch to another set of test activities. Such a conditional branch capability enables the tester to automatically perform an "if/then" diagnostic test on an IC in which a test result detected at any point during the test determines the future course of the test.

Claims7

Dependent claims

An apparatus for performing a test on an integrated circuit having a plurality of terminals, wherein the test is organized into a plurality of test segments, the apparatus comprising:

a trigger bus;
and
a plurality of tester channels interconnected by said trigger bus, each tester channel being connected to a separate terminal of said plurality of IC terminals and concurrently storing instructions for carrying out test activities at said separate terminal for each of said plurality of test segments,
wherein said test activities include generating a test signal and detecting events in an IC output signal,
wherein during one of said plurality of test segments, one of said plurality of tester channels transmits a trigger code concurrently to others of said plurality of tester channels via said trigger bus upon detecting a particular event in said IC output signal, and
wherein others of said plurality of tester channels respond to said trigger code by branching to and executing instructions for another one of said plurality of test segments.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/232,098Filed 15 Jan 1999
Granted: 28 Nov 2000
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G01R 31/31907
Tester configuration: modular tester, e.g. controlling and coordinating instruments in a bus based architecture
G01R 31/31917
Tester hardware, i.e. output processing circuits: stimuli generation or application of test patterns to the device under test [DUT]
G01R 31/3167
Testing of electronic circuits, e.g. by signal tracer: testing of combined analog and digital circuits
G01R 31/31922
Stimuli generation or application of test patterns to the device under test [DUT]: timing generation or clock distribution