Method for using wafer navigation to reduce testing times of integrated circuit wafers
AssigneeHeuristic Physics Laboratories, Inc.
InventorDavid Yepejian Lepejian
Life of this patent
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Abstract
A method for testing an integrated circuit wafer is described, wherein the wafer has a first plurality of dice defined thereon, and at least one die has at least one known defect. The method comprises the steps of selecting for testing a first die having a known defect; analyzing connectivity information and defect information relating to the first die, determining, based upon the analysis, a probability of failure for each known defect on the first die, and modifying the sequence of tests performed on the first die so that at least one test which directly relates to a known defect is performed prior to performing tests which are unrelated to a defect.
Claims15
A method for testing an integrated circuit wafer, the wafer having a plurality of dice defined thereon, at least one die having at least one known defect, as determined by inspection, the method comprising the steps of:
- selecting for testing a first die having a known defect;
- analyzing connectivity information and defect information relating to said first die;
- determining, based upon said analysis of said connectivity information and said defect information, a probability of failure for each known defect on said first die;
- and
- modifying the sequence of tests performed on said first die so that at least one test which directly relates to a known defect is performed prior to performing tests which are unrelated to a defect.
A method for testing an integrated circuit wafer, the wafer having a first plurality of dice defined thereon, at least one die having at least one known defect, as determined by inspection, the method comprising the steps of:
- selecting for testing a first die having a known defect;
- analyzing connectivity information and defect information relating to said first die;
- determining, based upon said analysis of said connectivity information and said defect information, a probability of failure for each known defect existing on said first die;
- and
- ranking, on said first die having a plurality of known defects, each known defect in decreasing probability of failure;
- modifying the sequence of tests performed on said first die so that one or more tests directly relating to said known defects are performed in an order corresponding to the results of said ranking step and prior to performing tests which are unrelated to a defect.
A method for controlling the testing of an integrated circuit wafer, the wafer having a first plurality of subregions defined thereon, at least one subregion within said plurality of subregions having at least one known defect, as determined by inspection, the method comprising the steps of:
- analyzing connectivity information and defect information relating to the at least one subregion having at least one known defect;
- determining, based upon said analysis, a probability of failure for each at least one known defect;
- and
- rejecting, prior to testing, any of the at least one subregions having at least one known defect if said known defect is determined to have an unacceptably high probability of failure.
Dependencies are inferred from the claim text.