Audio mute control signal generating circuit

An audio mute control signal generating circuit comprising:

• means for amplifying an audio input signal using a first differential operational amplifier stage and a second differential operational amplifier stage in cascaded arrangement with the first differential operational amplifier stage, to generate a first mute control zero-crossing clock signal and an inverted second mute control zero-crossing clock signal, wherein the first differential operational amplifier stage further has transistors operatively coupled for providing feedback to increase a commonmode voltage from the first differential operational amplifier stage to keep the cascaded second differential operational amplifier stage on during fluctuations of the audio input signal;
• and
• means, responsive to the mute control zero-crossing clock signal and a mute enable signal transition, for shifting the mute enable transition to align with a zero-crossing of the audio input signal, including means for receiving the first mute control zero-crossing clock signal, the inverted second mute control zero-crossing clock signal and the mute enable signal transition and for generating a mute control signal that represents a shifting of the mute enable transition to align with a zero-crossing of the audio input signal.