Digital phase lock loop with control for enabling and disabling synchronization
AssigneeNortel Networks Limited
InventorAndrew Homan
Life of this patent
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Abstract
The invention relates to methods and apparatus for synchronizing a local data clock with timing information from received data, during a fraction of a frame period. The apparatus includes a transition detect unit, a digital phase comparator, a phase regulator, and a control unit, for detecting the bit transitions of received data, determining the phase difference between timing information and a local data clock, advancing or retarding the local data clock, and enabling and disabling the synchronization in accordance with a predetermined rate.
Claims6
A digital phase locked loop (DPLL) for synchronizing a local data clock with timing information from received data, during a fraction of a frame period, comprising:
- a transition detect unit for detecting the bit transitions of said received data;
- a digital phase comparator electrically coupled to said transition detect unit for determining the phase difference between said timing information and said local data clock;
- a phase regulator electrically coupled to said digital phase comparator and a local clock source for advancing or retarding said local data clock;
- and
- a control unit for enabling and disabling said synchronizing in accordance with a predetermined rate, wherein said predetermined rate is a function of a predetermined disable period of time (Td), a predetermined enable period of time (Te), said local clock source (LCS), and said local data clock (LDC), thereby synchronizing said local data clock with timing information from received data, during a fraction of a frame period.
An apparatus for synchronizing a local data clock with timing information from received data, during a fraction of a frame period, comprising:
- transition detect means for detecting the bit transitions of said received data;
- digital phase comparator means electrically coupled to said transition detect means for determining the phase difference between said timing information and said local data clock;
- phase regulator means electrically coupled to said digital phase comparator means and a local clock source for advancing or retarding said local data clock;
- and
- control means for enabling and disabling a synchronizing in accordance with a predetermined rate, wherein said predetermined rate is a function of a predetermined disable period of time (Td), a predetermined enable period of time (Te), said local clock source (LCS), and said local data clock (LDC), thereby synchronizing said local data clock with timing information from received data, during a fraction of a frame period.
A method of synchronizing a local data clock with timing information from received data, during a fraction of a frame period, comprising:
- detecting the bit transitions of said received data;
- determining the phase difference between said timing information and said local data clock;
- advancing or retarding said local data clock;
- and
- enabling and disabling said synchronizing in accordance with a predetermined rate,
- wherein said predetermined rate is a function of a predetermined disable period of time (Td), a predetermined enable period of time (Te), a local clock source (LCS), and said local data clock (LDC), thereby synchronizing said local data clock with timing information from received data, during a fraction of a frame period.
Dependencies are inferred from the claim text.