Clock extraction circuit

A clock extraction circuit comprising:

• a first frequency divider circuit frequency-dividing received non-return-to-zero signals by a preset integer m;
• an edge detection circuit detecting transition points of an output of said first frequency divider circuit and producing transition point output signals;
• a voltage-controlled oscillator generating and outputting clock signal in a frequency range substantially equal to a transmission rate of the received non-return-to-zero signals;
• a second frequency divider circuit frequency-dividing output clock signals of said voltage-controlled oscillator by a preset integer n;
• a phase comparator phase-comparing the transition point output signals of said edge detection circuit and the clock signals frequency-divided by n by said second frequency divider circuit;
• and
• an absolute value circuit outputting an absolute value of an output of said phase comparator, wherein the second frequency divider circuit produces a divided frequency signal wherein a falling edge of the divided frequency signal should sometimes be detected for a correct phase error, and the absolute value circuit compensates for the phase comparison with the divided frequency signal.

A clock extraction circuit comprising:

• an edge detection circuit detecting transition points of received non-return-to zero signals and producing transition point output signals;
• a voltage-controlled oscillator generating and outputting clock signals in a frequency range substantially equal to the transmission rate of the received non-return-to-zero signals;
• a frequency divider circuit frequency-dividing output clock signals of said voltage-controlled oscillator by a preset integer n;
• a phase comparator phase-comparing the n-frequency-divided clock signals with the transition point output signals of the edge detection circuit;
• and
• an absolute value circuit outputting an absolute value of an output of said phase comparator, wherein the second frequency divider circuit produces a divided frequency signal wherein a falling edge of the divided frequency signal should sometimes be detected for a correct phase error, and the absolute value circuit compensates for the phase comparison with the divided frequency signal.

A clock extraction circuit comprising:

• a first frequency divider circuit frequency-dividing received non-return-to-zero signals by 2;
• an edge detection circuit detecting transition points of an output of said first frequency divider circuit and producing transition point output signals;
• a voltage-controlled oscillator generating and outputting clock signal in a frequency range substantially equal to a transmission rate of the received non-return-to-zero signals;
• a second frequency divider circuit frequency-dividing the clock signals generated by said voltage-controlled oscillator by 2;
• a phase comparator phase-comparing the transition point output signals of the edge detection circuit and the frequency-divided clock signals divided by the second frequency divider circuit;
• and
• an absolute value circuit outputting an absolute value of an output of said phase comparator, wherein the frequency divider circuit produces a divided frequency signal wherein a falling edge of the divided frequency signal should sometimes be detected for a correct phase error, and the absolute value circuit compensates for the phase comparison with the divided frequency signal.

A clock extraction circuit comprising;

• an edge detection circuit detecting transition points of received non-return-to-zero signals and producing transition point output signals;
• a voltage-controlled oscillator generating and outputting clock signals in a frequency range substantially equal to a transmission rate of the received non-return-to-zero signals;
• a frequency divider circuit frequency-dividing output clock signals of said voltage-controlled oscillator by 2;
• a phase comparator phase-comparing the transition point output signals of said edge detection circuit and the frequency-divided clock signals divided by said frequency divider circuit;
• and
• an absolute value circuit outputting an absolute value of an output of said phase comparator, wherein the frequency divider circuit produces a divided frequency signal wherein a falling edge of the divided frequency signal should sometimes detected for a correct phase error, and the absolute value circuit compensates for the phase comparison with the divided frequency signal.

A clock extraction circuit comprising:

• a first frequency divider circuit frequency-dividing received non-return-to-zero signals by a preset integer m;
• an edge detection circuit detecting transition points of an output of said first frequency divider circuit and producing transition point output signals;
• a voltage-controlled oscillator generating and outputting clock signals in a frequency range substantially equal to a transmission rate of the received non-return-to-zero signals;
• a second frequency divider circuit frequency-dividing output clock signals of said voltage-controlled oscillator by a preset integer n;
• a phase comparator phase-comparing the transition point output signals of said edge detection circuit and the clock signals frequency-divided by n said second frequency divider circuit:
• an absolute value circuit outputting an absolute value of an output of said phase comparator;
• wherein said absolute value circuit is formed so that
• one of complementary outputs of said phase comparator is entered to a base of a first bipolar transistor as one of complementary inputs;
• the other of said complementary outputs of said phase comparator is entered to a base of a second bipolar transistor as the other of said complementary inputs;
• an emitter of said first bipolar transistor is connected to an end of a first resistor;
• an emitter of said second bipolar transistor is connected to an end of a second resistor;
• the opposite end of said first resistor and the opposite end of said second resistor are connected to a collector of a third bipolar transistor;
• a collector of said first bipolar transistor and a collector of said second bipolar transistor are connected to an end of a third resistor;
• the opposite end of said third resistor is connected to a first source voltage;
• an emitter of said third bipolar transistor is connected to an end of a fourth resistor, the opposite end of which is connected to a second source voltage;
• a base of said third polar transistor is connected to a third source voltage;
• and
• collector terminals of said first and second bipolar transistors output a value proportionate to an absolute value of a difference between the one and the other of the complementary inputs in a state in which said third bipolar transistor operates in saturation.

A clock extraction circuit comprising:

• a first frequency divider circuit frequency-dividing received non-return-to-zero signals by a preset integer m;
• an edge detection circuit detecting transition points of an output of said first frequency divider circuit and producing transition point output signals;
• a voltage-controlled oscillator generating and outputting clock signals in a frequency range substantially equal to a transmission rate of the received non-return-to-zero signals;
• a second frequency divider circuit frequency-dividing output clock signals of said voltage-controlled oscillator by a preset integer n;
• a phase comparator phase-comparing the transition point output signals of said edge detection circuit and the clock signals frequency-divided by n said second frequency divider circuit;
• an absolute value circuit outputting an absolute value of an output of said phase comparator;
• wherein said absolute value circuit is formed so that
• one of complementary outputs of said phase comparator is entered to a base of a first bipolar transistor as one of complementary inputs;
• the other of said complementary outputs of said phase comparator is entered to a base of a second bipolar transistor as the other of said complementary inputs;
• an emitter of said first bipolar transistor is connected to an end of a first resistor;
• an emitter of said second bipolar transistor is connected to an end of a second resistor;
• the opposite end of said first resistor and the opposite end of said second resistor are connected to an end of a third resistor;
• a collector of said first bipolar transistor and a collector of said second bipolar transistor are connected to an end of a fourth resistor, the opposite end of which is connected to a first source voltage;
• the opposite end of said third resistor is connected to a second source voltage;
• and
• collector terminals of said first and second bipolar transistors output a value proportionate to the absolute value of a difference between the one and the other complementary inputs.

A clock extraction circuit for receiving non-return-to-zero signals for signal regeneration comprising:

• means for providing a first signal by frequency-dividing received non-return-to-zero signals by m, where m is a pre-set integer,
• means for detecting edges of the frequency-divided signals,
• means for providing a second signal by frequency-dividing a signal generated by a voltage-controlled oscillator at a frequency substantially equal to a transmission rate of the received non-return-to-zero signals by n, where n is a pre-set integer;
• phase comparator means for phase-comparing said first and second signals each other to extract synchronized clock signals;
• and
• an absolute value circuit outputting an absolute value of an output of said phase comparator means, wherein the means for providing a second signal by frequency dividing produces a divided frequency second signal wherein a falling edge of the divided frequency second signal should sometimes be detected for a correct phase error, and the absolute value circuit compensates for the phase comparison with the divided frequency second signal.