Symbol timing recovery based on adjusted, phase-selected magnitude values

In a digital communication receiver, a method of recovering symbol timing from an analog signal received from a channel which distorts said analog signal, said method comprising:

• generating, within a phase locked loop, a clock signal which defines symbol timing;
• converting, within said phase locked loop, said analog signal into a complex digital data stream having a complex sample for each symbol interval;
• separating, within said phase locked loop, magnitude attributes of said complex samples for each symbol interval from phase attributes of said complex samples so that said magnitude attributes are substantially insensitive to phase changes;
• identifying clock adjustment opportunities in response to said complex samples;
• generating, within said phase locked loop, a phase error estimate signal that adjusts said symbol timing defined by said clock signal in response to said separated magnitude attributes of said complex samples, said phase error estimate signal being updated in synchronism with said identified clock adjustment opportunities;
• and
• adjusting said phase error estimate signal to cause said phase locked loop to achieve a locked condition in the presence of distortion in said analog signal.

A symbol synchronizer for recovering symbol timing in a digital communication receiver which receives an analog signal configured as a stream of symbols from a channel which distorts said analog signal, said symbol synchronizer comprising:

• a clock generator for generating a clock signal that defines symbol timing;
• a converter, coupled to said clock generator, for converting said analog signal into first and second complex digital data streams, said second stream having samples representing said analog signal at instants delayed by a fraction of a symbol interval from instants represented by samples of said first stream;
• a first phase processor coupled to said converter, for identifying first clock adjustment opportunities in response to phase relationships exhibited by said first stream samples;
• a first magnitude processor, coupled to said converter and said first phase processor, for generating a first phase error estimate signal in response to magnitude relationships exhibited by said first stream samples, said first phase error estimate signal being updated in synchronism with said first identified clock adjustment opportunities;
• a second phase processor coupled to said converter, for identifying second clock adjustment opportunities in response to phase relationships exhibited by said second stream samples;
• a second magnitude processor coupled to said converter and said second phase processor, for generating a second phase error estimate signal in response to magnitude relationships exhibited by said second stream samples, said second phase error estimate signal being updated in synchronism with said second identified clock adjustment opportunities;
• and
• a summation circuit having an output coupled to said clock generator, a first input adapted to receive said first phase error estimate signal and a second input adapted to receive said second phase error estimate signal.