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US 6,154,509 AGranted
Data phase recovery system
AssigneeNatural MicroSystems Corporation
InventorWendell Bishop
Life of this patent
Estimating the term…
Abstract
Apparatus and method for processing serial data signals. In one general aspect, the method features receiving a first serial data signal having a clock frequency and phase, detecting a phase characteristic of the first serial data signal, and delaying the first serial data signal based on the phase characteristic of the first serial data signal to align at least one point in the first serial data signal with at least one point in a system clock signal.
Claims11
A clock recovery circuit, comprising:
- a data input line,
- a system clock line,
- a sync detector having a data input responsive to the data input line and having sync detection signal output wherein the sync detector is operative to employ discrete oversampling on an input data signal received on the data input line to provide noise immunity by requiring multiple identical oversamples both prior to and after a transition on the input data signal, and
- a variable delay element having a clock input responsive to the system clock, having a sync detection input responsive to the detection signal output of the sync detector, having a data input responsive to the data input line, and having a data output.
1 more element
A method of processing serial data signals, comprising:
- receiving a first serial data signal having a clock frequency and phase, oversampling received first serial data signal with a multiple of a system clock signal,
- detecting a phase characteristic of the first serial data signal by detecting a number of identical oversamples both before and after a transition in the serial data signal, and
- delaying the first serial data signal based on the phase characteristic of the first serial data signal to align at least one point in the first serial data signal with at least one point in a system clock signal.
Dependencies are inferred from the claim text.