Computer system with a semi-differential bus signaling scheme
AssigneeIntel Corporation
InventorsSanjay Dabral, Dilip K. Sampath, Alper Ilkbahar
Life of this patent
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Abstract
A computer system with a semi-differential bus-signaling scheme is described. The computer system includes a transmitter coupled to a common bus. The transmitter sends clock signals and a data signal to logic-comparing devices within a receiver. The logic-comparing devices compare the data signal to a reference voltage while comparing the clock signals to each other. After the comparison, the clock signals can be used to capture the data into a retiming circuit.
Claims15
A computer system comprising:
- a transmitter having a data output, a clock output and an inverted clock output;
- and
- a receiver having:
- a first comparator having a first input connected to the clock output and a second input connected to the inverted clock output;
- a second comparator having a third input connected to the data output and a fourth input connected to a reference voltage output;
- a third comparator having a fifth input connected to the inverted clock output and a sixth input connected to the clock output;
- and
- a retiming circuit having:
- a data input connected to an output of the second comparator;
- and
- a clock input connected to an output of the first comparator.
A computer system having a common bus, the computer system comprising:
- a first device that is one of a group consisting of a microprocessor and a chipset, the first device having a data output, a clock output, and an inverted clock output;
- and
- a second device that is one of the group consisting of a microprocessor and a chipset, the second device having:
- a first comparator having a first input connected to the clock output and a second input connected to the inverted clock output;
- a second comparator having a third input connected to the data output and a fourth input connected to a reference voltage output;
- a third comparator having a fifth input connected to the inverted clock output and a sixth input connected to clock output;
- and
- a retiming circuit having:
- a data input connected to an output of the second comparator;
- and
- a clock input connected to an output of the first comparator.
A computer system having a semi-differential bus signaling scheme, the computer system comprising:
- a first device that is one of a group consisting of a microprocessor and a chipset, the first device having a data output, a clock output, and an inverted clock output;
- and
- a second device that is one of the group consisting of a microprocessor and a chipset, the second device having:
- a first differential amplifier having a first positive input connected to the clock output and a first negative input connected to the inverted clock output;
- a second differential amplifier having a second positive input connected to the inverted clock output and a second negative input connected to the clock output;
- a third differential amplifier having a third positive input connected to the data output and a third negative input connected to a reference voltage output;
- and
- a retiming circuit having:
- a data input connected to an output of the third differential amplifier;
- a clock input connected to an output of the first differential amplifier;
- and
- an inverted clock input connected to an output of the second differential amplifier.
A computer system comprising:
- a transmitter having a data output, a clock output, and an inverted clock output;
- and
- a receiver having:
- a first comparator having a first input connected to the clock output and a second input connected to the inverted clock output;
- a second comparator having a third input connected to the data output and a fourth input connected to a reference voltage output;
- a first reset capable latch having:
- a first reset input;
- and
- a clock input connected to an output of the first comparator;
- a retiming circuit having:
- a data input connected to an output of the second comparator;
- and
- a clock input connected to an output of the first reset capable latch.
Dependencies are inferred from the claim text.