Method and system for analog to digital conversion

A conversion system for converting an analog signal to a digital signal in a communications system, the conversion system comprising:

• an oversampled analog-to-digital converter modulator for receiving an oversampling-clock signal and a transmitted analog signal, the oversampled analog-to-digital converter modulator operable to sample the analog signal and to convert the analog signal to a first digital signal;
• a time adjustor coupled to the oversampled analog-to-digital converter modulator for receiving the first digital signal and a first adjustment signal, and for producing an output digital signal;
• and
• a digital signal processor unit coupled to the time adjustor for receiving the output digital signal and performing timing recovery thereon to determine if any adjustment of the time adjustor is required to minimize phase error and/frequency error, and for producing the first adjustment signal;
• wherein the time adjustor comprises:
• a decimation filter coupled to the oversampled analog-to-digital converter modulator for receiving the first digital signal and producing the output digital signal having more bits of precision, the decimation filter having a first portion and a second portion;
• a clock control coupled to the digital signal processing unit for receiving the first adjustment signal and producing a first clock signal, the clock control coupled to the first portion of the decimation filter for delivering the first clock signal thereto;
• a clock divider coupled to the clock control for receiving the first clock signal and dividing it by an oversampling factor to produce a second clock signal, the clock divider coupled to the second portion of the decimation filter for delivering the second clock signal thereto;
• and
• wherein the clock control and clock divider are operable to adjust the output digital signal in response to the first adjustment signal.

A conversion system for converting an analog signal to a digital signal in a communications system, the conversion system comprising:

• an oversampled analog-to-digital converter modulator for receiving an oversampling-clock signal and a transmitted analog signal, the oversampled analog-to-digital converter modulator operable to sample the analog signal and to convert the analog signal to a first digital signal;
• a time adjustor coupled to the oversampled analog-to-digital converter modulator for receiving the first digital signal and a first adjustment signal, and for producing an output digital signal;
• and
• a digital signal processor unit coupled to the time adjustor for receiving the output digital signal and performing timing recovery thereon to determine if any adjustment of the time adjustor is required to minimize phase error and frequency error, and for producing the first adjustment signal;
• wherein the time adjustor comprises:
• a decimation filter coupled to the oversampled analog-to-digital converter modulator for receiving the first digital signal and producing a first intermediate digital signal having more bits of precision, the decimation filter having a first portion and a second portion;
• a clock control coupled to the digital signal processing unit for receiving the first adjustment signal and producing a first clock signal, the clock control coupled to the first portion of the decimation filter for delivering the first clock signal thereto;
• a clock divider coupled to the clock control for receiving the first clock signal and dividing it by an oversampling factor to produce a second clock signal, the clock divider coupled to the second portion of the decimation filter for delivering the second clock signal thereto;
• wherein the clock control and clock divider are operable to adjust the first intermediate digital signal in response to the first adjustment signal;
• wherein the digital signal processor unit is further operable to produce a second adjustment signal for fine tuning timing;
• and
• an interpolation filter coupled between the decimation filter and the digital signal processor unit for receiving the first intermediate digital signal from the decimation filter and for receiving the second adjustment signal from the digital signal processing unit, and operable to generate therefrom the output digital signal with the output digital signal more precisely adjusted than the second digital signal.

A conversion system for converting an analog signal to a digital signal in a communications system, the conversion system comprising:

• an oversampled analog-digital converter modulator for receiving an oversampling-clock signal and a transmitted analog signal, the oversampled analog-to-digital converter modulator operable to sample the analog signal and to convert the analog signal to a first digital signal;
• a decimation filter coupled to the oversampled analog-to-digital converter modulator for receiving the first digital signal and producing a second digital signal having more bits of precision, the decimation filter having a first portion and a second portion;
• a clock control coupled to the oversampled analog-to-digital converter modulator for controlling sample timing of the oversampled analog-to-digital converter modulator;
• a digital signal processing unit coupled to the decimation filter for receiving the second digital signal and performing a timing recovery algorithm thereon to determine if any adjustment of the clock control is required to minimize phase error and frequency error, and for producing a first adjustment signal based on the results of the timing recovery algorithm;
• the clock control coupled to the digital signal processing unit for receiving the first adjustment signal and producing a first clock signal, the clock control coupled to the first portion of the decimation filter for delivering the first clock signal thereto;
• a clock divider coupled to the clock control for receiving the first clock signal and dividing it by an oversampling factor to produce a second clock signal, the clock divider coupled to the second portion of the decimation filter for delivering the second clock signal thereto;
• and
• wherein the second digital signal is the output signal for the conversion system and;
• an interpolation filter coupled between the decimation filter and the digital signal processor unit for receiving the second digital signal from the decimation filter and a second adjustment signal generated by the digital signal processing unit, the interpolation filter having a plurality of subfilters, the interpolation filter operable to generate a third digital signal using Farrow's method, the third digital signal being more precisely adjusted than the second digital signal and being the output signal for the conversion system.

A method of timing recovery comprising the steps of:

• receiving a transmitted analog signal;
• converting the analog signal to a first digital signal with an oversampling analog-to-digital converter modulator;
• performing a time adjustment with a timing adjustor on the first digital signal to produce an output digital signal having more bits of precision than the first digital signal and less timing error;
• performing timing recovery on the output digital signal and producing a first adjustment signal based on the results of the timing recovery;
• and
• modifying the time adjustor based on the first adjustment signal to minimize timing error;
• and
• wherein the step of performing a time adjustment comprises the steps of:
• storing the first digital signal in a plurality of delay elements, wherein the plurality of delay elements are for receiving the first digital signal and holding the first digital signal for different intervals;
• and
• selectively accessing one of the plurality of delay elements with a multiplexor coupled thereto and based on the first adjustment signal to obtain the first digital signal for a desired delay interval;
• and
• filtering the first digital signal for the desired delay interval with a decimation filter to produce the output digital signal having more bits of precision than the first digital signal.

A method of timing recovery comprising the steps of:

• receiving a transmitted analog signal;
• converting the analog signal to a first digital signal with an oversampling analog-to-digital converter modulator;
• performing a time adjustment with a timing adjustor on the first digital signal to produce an output digital signal having more bits of precision than the first digital signal and less timing error;
• performing timing recovery on the output digital signal and producing a first adjustment signal based on the results of the timing recovery;
• modifying the time adjustor based on the first adjustment signal to minimize timing error;
• wherein the step of performing a time adjustment comprises:
• producing a first clock signal based on the first adjustment signal;
• delivering the first clock signal to a first portion of a dedicator filter;
• producing a second clock signal by dividing the first clock signal by an oversampling factor;
• delivering the second clock signal to a second portion of the dedicator filter;
• and
• skipping a cycle in the first clock signal if the sampling is occurring too early and generating a duplicate clock pulse in the first clock signal if the sampling is occurring too late, to produce the output signal.