Method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory
AssigneeATI Technologies, Inc.
InventorRajesh G. Shakkarwar
Life of this patent
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Abstract
A method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory is provided. While memory accessing agents, such a microprocessors, typically have a fixed memory access size (e.g., number of bits or bytes exchanged with a memory device in a single operation), DDR memory provides twice the memory burst capability of SDRAM. A method and apparatus is provided to allow memory access agents to exchange data with both SDRAM and DDR memory. Smaller groups of data may be combined or larger groups of data may be separated to allow compatibility. Buffering is provided to accommodate proper timing. Both SDRAM and DDR memory may be used simultaneously.
Claims34
A method for controlling a memory access to a first memory device comprising the steps of:
- determining a memory burst capability of the first memory device;
- determining a memory access size for at least one agent;
- determining whether the memory burst capability and the memory access size are compatible;
- when the memory burst capability and the memory access size are not compatible, effectively adjusting within a memory controller the memory burst capability to be compatible with the memory access size.
Apparatus comprising:
- a memory accessing agent having a memory access size;
- a first memory device having a first memory burst capability;
- and
- a memory controller, the memory controller operatively coupled to the memory accessing agent and to the first memory device, the memory controller effectively adjusting the first memory burst capability to be compatible with the memory access size.
Apparatus comprising:
- a central processing unit (CPU);
- an accelerated graphics port (AGP) graphics master device;
- a PCI interface master device;
- a memory device;
- a system clock generator;
- the system clock generator operatively coupled to the CPU and providing a system clock signal to the CPU;
- and
- a memory controller, the memory controller operatively coupled to the CPU, the AGP graphics master device, the PCI interface master device, the memory device, and the system clock generator, the memory controller effectively adapting a memory burst capability of the memory device to a memory access size of the CPU, the AGP graphics master device, or the PCI interface master device.
Dependencies are inferred from the claim text.