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US 6,154,418 AGranted
Write scheme for a double data rate SDRAM
AssigneeMicron Technology, Inc.
InventorWen Li
Life of this patent
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AssigneeMicron Technology, Inc.
InventorWen Li
Estimating the term…
A double data rate (DDR) synchronous dynamic random access memory (SDRAM) device with at least one memory bank is disclosed. Each memory bank is divided into two independent and simultaneously accessible memory planes. Input data aligned with the rising edge of a data strobe (DQS) and input data aligned with the falling edge of the DQS are separately latched coincident with the respective edges of the DQS. Using an internal clock, the latched input data is re-aligned and simultaneously sent to both planes of an addressed memory bank at the rising edge of the internal clock. With this configuration, the internal processing of the SDRAM is unaffected by latency variations of the DQS.
A method of writing data into a memory device, the memory device comprising at least one memory bank, said memory bank being divided into at least two planes of memory cells, said method comprising the steps of:
A method of writing data into a memory device, the memory device comprising at least one memory bank, said memory bank being divided into at least two planes of memory cells, said method comprising the steps of:
A method of writing data into a synchronous dynamic random access memory (SDRAM) device, the SDRAM comprising at least one memory bank divided into at least two planes of memory cells, said method comprising the steps of:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: output…
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: for memories with random access ports…
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data input circuits, e.g. write amplifiers, data…
Static stores
Term ended 3 Dec 2018 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to the field of semiconductor memory devices and, more particularly to a write scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices.
2. Description of the Related Art
The foregoing and other advantages and features of the invention will become more apparent from the detailed description of the preferred embodiments of the invention given below with reference to the accompanying drawings in which:
FIG. 1 illustrates a synchronous dynamic random access memory (SDRAM) constructed in accordance with a preferred embodiment of the present invention;
FIG. 2 illustrates an exemplary configuration of memory banks utilized in the SDRAM of FIG. 1;
FIG. 1 illustrates a SDRAM 10 constructed in accordance with a preferred embodiment of the present invention. The SDRAM 10 includes a control circuit 12, addressing circuit 40, input/output circuit 30, memory banks 20, sense amplifier circuits 16, column decoders 18 and row decoders 14. In a preferred embodiment, four memory banks 20, sense amplifier circuits 16, column decoders 18 and row decoders 14 are used, but for convenience purposes only, FIG. 1 illustrates one memory bank 20, sense amplifier circuit 16, column decoder 18 and row decoder 14. In a preferred embodiment, four memory banks 20, are used, but it must be noted that the present invention can utilize, for example, one, two, four, eight or more memory banks 20, etc. The row and column decoders 14, 18, addressing circuit 30 and input/output logic circuit 30 comprise a write path circuit 32 providing a data path for writing data into the banks 20 from an external device (through input/output pins DQ0-DQ7). It must be noted that the illustrated configuration of the write path circuit 32 is but one of many possible configurations and the invention is not to be so limited to the specific circuit illustrated in FIG. 1.
Preferably, the SDRAM 10 contains eight input/output pins DQ0-DQ7. This is referred to as a ".times.8" device since eight bits are input or output at one time. It must be noted that the SDRAM 10 can also be configured to have four input/output pins (i.e., a ".times.4" device), sixteen input/output pins (i.e., a ".times.16" device) or more.
Each of the memory banks 20 contain memory cells arranged in rows and columns and are connected to a respective row decoder 14 and sense amplifier circuit 16. Preferably, the size of the memory banks 20 are at least 16 M each (that is, 16,777,216 individual memory cells or "bits"), although any size bank 20 can be used.