Integrated circuit memory devices having synchronous wave pipelining capability and methods of operating same

An integrated circuit memory device, comprising:

• a data output register that is responsive to i through j consecutive register input control signals and i through j register output control signals, where "i" and "j" are integers;
• a column decoder circuit that generates i through j column select signals in sequence during respective i through j consecutive periods of an internal clock signal;
• means, responsive to the i through j column select signals, for providing read data to said data output register during i+.alpha. through j+.alpha. consecutive periods of the internal clock signal, where .alpha. is a positive integer;
• and
• a pipelined register input control circuit that generates the i through j consecutive register input control signals in-sync with the internal clock signal during the i+.alpha. through j+.alpha. consecutive periods thereof.

A synchronous semiconductor memory device comprises:

• a memory cell array for storing data;
• a read circuit for sequentially reading out data in the memory cell array in synchronization with a clock signal during a read operation;
• a register having a plurality of latch circuits connected in parallel to each other, for sequentially storing the data from the read circuit in corresponding latch circuits in response to register input control signals during the read operation;
• a register control circuit for generating the register input control signals in synchronization with the clock signal during the read operation, the register control circuit generating a register input control signal in synchronization with the clock signal of i-th clock cycle in order that read data corresponding to (i-1)th clock cycle is stored in a corresponding latch circuit in synchronization with the clock signal of i-th clock cycle, where "i" is an integer.

A synchronous semiconductor memory device comprising:

• an array of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells each arranged in intersections of the word lines and the bit lines, the bit lines being composed of a plurality of bit line pairs;
• a row selection circuit for selecting one from the word lines during a read operation;
• a column selection circuit for selecting a pair of bit lines from the bit line pairs in response to a column selection line enable signal in synchronization with the clock signal of i-th clock cycle, and for making a bit line pair selected at (i-1)th clock cycle inactivated in response to a column selection line disable signal in synchronization with the clock signal of i-th clock cycle, where "i" is an integer;
• a column selection line control circuit for producing the column selection line enable and disable signals in response to the clock signal at every clock cycle during the read operation;
• a sense amplifier circuit for sequentially sensing data corresponding to bit line pairs selected in order by the column selection circuit among the data stored in memory cells associated with the selected word line;
• a register having a plurality of latch circuits connected in parallel with each other, for successively storing the read data from the read circuit in corresponding latch circuits in response to register input control signals during the read operation;
• and
• a register input control circuit for sequentially generating the register input control signals in synchronization with the clock signal during the read operation,
• wherein the register input control circuit produces a register input control signal in synchronization with the clock signal of i-th clock cycle in order that read data corresponding to (i-1)th clock cycle is stored in a corresponding latch circuit in synchronization with the clock signal of i-th clock cycle.