Column address decoder for two bit prefetch of semiconductor memory device and decoding method thereof

A semiconductor memory device, comprising:

• a memory cell array including a plurality of memory cells for storing data and redundancy memory cells for replacing poor memory cells among the memory cells;
• a plurality of bit line pairs connected to the memory cells;
• a plurality of input and output line pairs;
• a plurality of switching means connected between the bit line pairs and the input and output line pairs;
• an even predecoder for receiving as an input the less significant bits of the address input from the outside and predecoding the less significant bits when the least significant bit is in a first logic state;
• an inverting decoder for reproducing the less significant bits of the external address corresponding to the address predecoded by the even predecoder;
• and
• a redundancy enable signal generating portion for generating a redundancy enable signal and receiving the output of the inverting decoder.

An integrated circuit memory device, comprising:

• an address predecoder that generates predecoded address signals in response to an applied address, said address predecoder comprising an even predecoder, an odd predecoder and a main predecoder;
• and
• a main decoder that receives the predecoded address signals, said main decoder comprising:
• an even decoder that receives predecoded address signals generated by the even predecoder and the main predecoder;
• and
• an odd decoder that receives predecoded address signals generated by the odd predecoder and the main predecoder.