Internal clock generation circuit of semiconductor device and method for generating internal clock

An internal clock generation circuit for a semiconductor device comprising:

• a clock buffer for receiving an external clock signal and converting a voltage level of the external clock signal;
• an internal clock generation unit for receiving the output of the clock buffer and generating an internal clock signal responsive to a control signal;
• a chip selection buffer for receiving a chip selection signal, activating the semiconductor device responsive to the chip selection signal, and converting a voltage level of the chip selection signal;
• and
• an internal clock control unit for receiving the output of the chip selection buffer and generating the control signal;
• wherein the internal clock signal is disabled when the control signal is disabled, and the internal clock signal is enabled when the control signal is enabled and at the same time the external clock signal is enabled;
• and
• wherein the internal clock generation unit comprises:
• a plurality of inverters connected in series with the output of the clock buffer for delaying and inverting the output of the clock buffer;
• a first logic gate for generating an output signal responsive to the output of the last one of the inverters and the output of the clock buffer;
• and
• a second logic gate for receiving the output of the first logic gate and the control signal, and generating the internal clock signal only when the control signal is enabled.

An internal clock generation circuit for a semiconductor device comprising:

• a clock buffer for receiving an external clock signal and converting a voltage level of the external clock signal;
• an internal clock generation unit for receiving the output of the clock buffer and generating an internal clock signal responsive to a control signal;
• a chip selection buffer for receiving a chip selection signal, activating the semiconductor device responsive to the chip selection signal, and converting a voltage level of the chip selection signal;
• and
• an internal clock control unit for receiving the output of the chip selection buffer and generating the control signal;
• wherein the internal clock signal is disabled when the control signal is disabled, and the internal clock signal is enabled when the control signal is enabled and at the same time the external clock signal is enabled;
• and
• wherein the internal clock control unit comprises:
• a plurality of inverters connected in series with the output of the chip selection buffer for delaying the output of the chip selection buffer;
• and
• a third logic gate for receiving the output of the last one of the inverters and the output of the chip selection buffer, and generating the control signal.

A method for generating an internal clock for a semiconductor device to which an external clock signal, a chip selection signal and a command are applied, wherein the chip selection signal is a signal for enabling and disabling the device, the method comprising the steps of:

• a) inputting the command and enabling the chip selection signal;
• b) enabling the external clock signal;
• c) generating a control signal which is enabled when the chip selection signal is enabled;
• d) generating an internal clock signal which is enabled when the control signal is enabled and at the same time the external clock signal is enabled,
• wherein the internal clock signal is not generated when the control signal is disabled.

A method for generating an internal clock for a semiconductor device to which an external clock signal, a chip selection signal and a command are applied, the method comprising the steps of:

• a) inputting the command and enabling the chip selection signal;
• b) enabling the external clock signal;
• c) generating a control signal which is enabled when the chip selection signal is enabled;
• d) generating an internal clock signal which is enabled when the control signal is enabled and at the same time the external clock signal is enabled,
• wherein the internal clock signal is not generated when the control signal is disabled
• wherein the command is for reading/writing data, and wherein said step c) further comprises the steps of:
• enabling a column address signal;
• and
• enabling a latency signal, and wherein the control signal is enabled when the column address signal and the latency signal are enabled, and the control signal is disabled when the latency signal, the control signal and the column address signal are disabled.

An internal clock generation circuit for a semiconductor device comprising:

• an internal clock generation unit for generating an internal clock signal responsive to an external clock signal and a control signal, wherein the internal clock generation unit only generates the internal clock signal when the control signal is enabled;
• and
• an internal clock control unit coupled to the internal clock generation unit for generating the control signal responsive to a chip selection signal;
• wherein the internal clock control unit:
• enables the control signal when the chip selection signal is enabled;
• delays a period of time after the chip selection signal is disabled;
• and
• disables the control signal after delaying the period of time.