Method for designing a memory tile for use in a tiled memory
OwnerMichael L. Longwell, William Daune Atwell +1inventors
InventorsMichael L. Longwell, William Daune Atwell, Jeffrey Van Myers
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Abstract
A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c', 32c").
Claims244
A method for designing a memory tile for use in a tiled memory, comprising the steps of:
- designing a memory cell;
- arranging a plurality of said memory cells in a cell array;
- determining the charge requirements of said cell array;
- designing a charge source to supply said charge requirements;
- and
- integrating said charge source and said cell array to form said memory tile.
A method for designing an integrated circuit having a memory tile in a tiled memory, comprising the steps of:
- designing a memory cell;
- arranging a plurality of said memory cells in a cell array;
- determining the charge requirements of said cell array;
- designing a charge source to supply said charge requirements;
- and
- integrating said charge source and said cell array to form said memory tile in said tiled memory of said integrated circuit.
Dependencies are inferred from the claim text.