Microcomputer and microprocessor having flash memory operable from single external power supply

A microcomputer comprising a semiconductor substrate incorporating a flash memory capable of being erased and programmed electrically and a central processing unit capable of accessing said flash memory, said microcomputer operating on a single power supply voltage supplied to an external power supply terminal of said semiconductor substrate;

• wherein said flash memory includes:
• a constant voltage generating circuit which, using a reference voltage with a low dependency on a power supply voltage, outputs a voltage lower in level than said single power supply voltage;
• boosting means for boosting the voltage output by said constant voltage generating means;
• and
• switching, means for switching halfway through a boosting operation, a substrate bias voltage common to MOS transistors connected to boosting nodes of said boosting means.

A microcomputer comprising a semiconductor substrate incorporating a flash memory capable of being erased and programmed electrically and a central processing unit capable of accessing said flash memory, said microcomputer operating on a single power supply voltage supplied to an external power supply terminal of said semiconductor substrate;

• wherein said flash memory includes:
• a power supply circuit for generating a high voltage for programming and erasure through a boosting operation;
• and
• a control register for controlling said flash memory, said control register including a programming enable bit and a protect bit, said programming enable bit enabling either erasure or programming when set to a predetermined value, said protect bit being set in accordance with an external terminal status, so that the setting of said programming enable bit to said predetermined value is enabled only if said protect bit is set to a predetermined value.

A microcomputer comprising a semiconductor substrate incorporating a flash memory capable of being erased and programmed electrically and a central processing unit capable of accessing said flash memory, said microcomputer operating on a single power supply voltage supplied to an external power supply terminal of said semiconductor substrate;

• wherein said flash memory includes:
• a memory cell array made of a plurality of memory cell transistors each having a control gate connected to a word line, a drain connected to a bit line, and a source connected to a source line;
• a boosting circuit for generating a high voltage for programming and erasure on said memory cell transistors;
• an address decoder for generating a word line selection signal based on an address signal;
• a word driver circuit for establishing a word line selection level in effect upon a read operation as a first polarity with respect to a ground potential, said word driver circuit further establishing a word line selection level in effect upon a write operation as a second polarity with respect to the ground potential;
• and
• timing control means acting upon a start and an end of a write operation to force all word lines to the ground potential, to invert logically the polarity of the selection level for said word line selection signal for said address decoder, and to switch operating power supplies of said word driver.

A semiconductor integrated circuit device comprising a semiconductor substrate incorporating a non-volatile memory capable of being erased and programmed electrically and a central processing unit capable of accessing said non-volatile memory, said semiconductor integrated circuit device operating on a single power supply voltage supplied to an external power supply terminal of said semiconductor substrate;

• wherein said non-volatile memory includes:
• a voltage clamp circuit which, using a reference voltage with a low dependency on a power supply voltage, clamps an output voltage to a first voltage lower in level than said single power supply voltage;
• a boosting circuit which boosts the voltage output by said voltage clamp circuit to a positive aid a negative high voltage;
• and
• a plurality of non-volatile memory cells erased and programmed by use of the positive and negative high voltages output by said boosting circuit.

A microcomputer comprising a semiconductor substrate incorporating a flash memory capable of being erased and programmed electrically and a central processing unit capable of accessing said flash memory, said microcomputer operating on a single power supply voltage supplied to an external power supply terminal of said semiconductor substrate;

• wherein said flash memory includes:
• a constant voltage generating circuit which, using a reference voltage with a low dependency on a power supply voltage, outputs a voltage lower in level than said single power supply voltage;
• a boosting circuit which boosts the voltage output by said constant voltage generating circuit;
• and
• a switching circuit which switches, halfway through a boosting operation, a substrate bias voltage common to MOS transistors connected to boosting nodes of said boosting circuit.

A microcomputer comprising a semiconductor substrate incorporating a flash memory capable of being erased and programmed electrically and a central processing unit capable of accessing said flash memory, said microcomputer operating on a single power supply voltage supplied to an external power supply terminal of said semiconductor substrate;

• wherein said flash memory includes:
• a power supply circuit which generates a high voltage for programming and erasure through a boosting operation;
• and
• a control register which controls said flash memory, said control register including a programming enable bit and a protect bit, said programming enable bit enabling either erasure or programming when set to a predetermined value, said protect bit being set in accordance with an external terminal status, so that the setting of said programming enable bit to
• said predetermined value is enabled only if said protect bit is set to a predetermined value.

A microcomputer comprising a semiconductor substrate incorporating a flash memory capable of being erased and programmed electrically and a central processing unit capable of accessing said flash memory, said microcomputer operating on a single power supply voltage supplied to an external power supply terminal of said semiconductor substrate;

• wherein said flash memory includes:
• a memory cell array made of a plurality of memory cell transistors each having a control gate connected to a word line, a drain connected to a bit line, and a source connected to a source line;
• a boosting circuit which generates a high voltage for programming and erasure on said memory cell transistors;
• an address decoder which generates a word line selection signal based on an address signal;
• a word driver circuit which establishes a word line selection level in effect upon a read operation as a first polarity with respect to a ground potential, wherein said word driver circuit further establishes a word line selection level in effect upon a write operation as a second polarity with respect to the ground potential;
• and
• a timing control circuit which acts upon a start and an end of a write operation to force all word lines to the ground potential, to invert logically the polarity of the selection level for said word line selection signal for said address decoder, and to switch operating power supplies of said word driver.