Self row-identified hidden refresh circuit and refresh method thereof

Abstract

A self row-identified hidden refresh circuit for refreshing a pseudo SRAM comprises a latchable burst array. The latchable burst array is composed of several latchable burst units, equipped respectively with a selector, delay elements and a state recording device. The selector selectively outputs a refresh pulse in accordance with the registered state of the state recording device. The refresh pulse is sequentially delayed by passing through the delay elements to refresh several rows of the pseudo SRAM. The state recording device records a first state before the refresh pulse enters the latchable burst units, a second state after the refresh pulse enters the latchable burst units, and the first state when the refresh pulse leaves the latchable burst units. In certain embodiments, the selector may include a multiplexer and the state recording device may include a SR flip-flop.

Dependencies are inferred from the claim text.