US 6,154,407 AGranted

First in first out memory circuit

AssigneeOki Electric Industry Co., Ltd.

InventorKenjiro Matoba

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Abstract

A first-in, first-out memory circuit includes first and second memory part respectively having first and second address locations each of which has a first word length, a write address counter outputting a write address signal and a memory part selection signal to the first and second memory parts in response to a word length selection signal, and a memory part enable circuit which is coupled between the write address counter and the first and second memory parts and receives the memory part selection signal. The memory circuit also includes a data bus which is applied with the input data and which includes a first data bus having the first word length and a second data bus having the first word length, and a data input part which is coupled between the data bus and the first and second memory parts.

Claims8

Dependent claims

A first-in, first-out memory circuit for storing data according to a data length of an input data applied to a data bus, said memory circuit comprising:

a first memory part which has a plurality of first address locations each having a first word length and each storing a data therein in response to an enable signal and a write signal, and which has a first input port for receiving the input data applied to the data bus and a first output port for outputting the data stored in the first address locations;
a second memory part which has a plurality of second address locations each having the first word length and each storing a data therein in response to the enable signal and the write address signal, and which has a second input port for receiving the input data applied to the data bus and a second output port for outputting the data stored in the second address locations, wherein each of the second address locations corresponds to the respective first address locations;
a write address counter which outputs the write address signal designating the first and second address locations and a memory part selection signal to said first and second memory parts in response to a word length selection signal, wherein the word length selection signal is a first voltage which designates a first data mode when the data length of the input data is not greater than the first word length, and wherein the word length selection signal is a second voltage which designates a second data mode when the data length of the input data is greater than the first word length;
a memory part enable circuit, coupled between said write address counter and said first and second memory parts, which receives the memory part selection signal and the word length selection signal, which outputs the enable signal to said first and second memory parts alternately in the first data mode, and which outputs the enable signal to said first and second memory parts simultaneously in the second data mode;
said data bus, applied with the input data, which includes a first data bus having the first word length and a second data bus having the first word length;
and
a data input part, coupled between said data bus and the first and second input ports, which transfers the input data applied to the second data bus to the first and second input ports in the first data mode, and which transfers the input data applied to the first and second data buses to the first and second input ports respectively in the second data mode.

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Dependencies are inferred from the claim text.

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Abstract

A first-in, first-out memory circuit for storing data according to a data length of an input data applied to a data bus, said memory circuit comprising:

a first memory part which has a plurality of first address locations each having a first word length and each storing a data therein in response to an enable signal and a write signal, and which has a first input port for receiving the input data applied to the data bus and a first output port for outputting the data stored in the first address locations;
a second memory part which has a plurality of second address locations each having the first word length and each storing a data therein in response to the enable signal and the write address signal, and which has a second input port for receiving the input data applied to the data bus and a second output port for outputting the data stored in the second address locations, wherein each of the second address locations corresponds to the respective first address locations;
a write address counter which outputs the write address signal designating the first and second address locations and a memory part selection signal to said first and second memory parts in response to a word length selection signal, wherein the word length selection signal is a first voltage which designates a first data mode when the data length of the input data is not greater than the first word length, and wherein the word length selection signal is a second voltage which designates a second data mode when the data length of the input data is greater than the first word length;
a memory part enable circuit, coupled between said write address counter and said first and second memory parts, which receives the memory part selection signal and the word length selection signal, which outputs the enable signal to said first and second memory parts alternately in the first data mode, and which outputs the enable signal to said first and second memory parts simultaneously in the second data mode;
said data bus, applied with the input data, which includes a first data bus having the first word length and a second data bus having the first word length;
and
a data input part, coupled between said data bus and the first and second input ports, which transfers the input data applied to the second data bus to the first and second input ports in the first data mode, and which transfers the input data applied to the first and second data buses to the first and second input ports respectively in the second data mode.

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