Dynamic random access memory capable of simultaneously writing identical data to memory cells

A semiconductor memory comprising:

• a plurality of bit line pairs each comprising a first bit line and a second bit line;
• a plurality of memory cells each located at an intersection between one of the first bit line and the second bit line of each of the bit line pairs and a selected word line;
• a data line pair comprising a first data line and a second data line;
• a plurality of column switches each connected between each of the bit line pairs and the data line pair;
• an input/output circuit connected at one end of the data line pair;
• and
• a column decoder, connected to the column switches, for turning on one of the column switches in a normal-write mode, and turning on two or more of the column switches in a block-write mode,
• wherein of said memory cells, the number of memory cells connected to the first bit line is equal to the number of memory cells connected to the second bit line.

A semiconductor memory comprising:

• a first bit line pair comprising a first bit line and a second bit line;
• a first memory cell located at an intersection between a first word line and the first bit line;
• a second memory cell located at an intersection between a second word line and the second bit line;
• a second bit line pair comprising a third bit line and a fourth bit line, the second bit line being located between the third bit line and the fourth bit line, the third bit line being located between the first bit line and the second bit line;
• a third memory cell located at an intersection between the second word line and the third bit line;
• a fourth memory cell located at an intersection between the first word line and the fourth bit line;
• a data line pair comprising a first data line and a second data line;
• a first column switch comprising a first transistor connected between the first bit line and the first data line and a second transistor connected between the second bit line and the second data line;
• a second column switch comprising a third transistor connected between the third bit line and the first data line and a fourth transistor connected between the fourth bit line and the second data line;
• an input/output circuit connected to one end of the data line pair;
• and
• a column decoder connected to the first and second column switch, for turning on one of the first column switch and the second column switch in a normal-write mode, and turning on both the first column switch and the second column switch in a block-write mode.