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US 6,154,405 AGranted
Semiconductor memory device having a dummy cell resetting the bit lines to a reset potential that is based on data read in a previous read data
AssigneeFujitsu Limited
InventorsYoshihiro Takemae, Masao Taguchi, Masao Nakano, Hirohiko Mochizuki, Hiroyoshi Tomita, Yasurou Matsuzaki, Tadao Aikawa
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.
Claims24
A semiconductor memory device comprising:
- memory cells;
- word lines connected to the memory cells;
- bit lines connected to the memory cells;
- and
- a first circuit which resets the bit lines to a reset potential for the next read cycle depending on data read to the bit lines in a previous read cycle.
2 more elements
A semiconductor memory device comprising:
- memory cells;
- word lines connected to the memory cells;
- pairs of bit lines connected to the memory cells;
- sense amplifiers connected to the pairs of bit lines;
- pairs of data buses coupled the sense amplifiers via data input/output circuits;
- and
- a circuit which sets the pairs of data buses to a floating state,
- wherein, when data includes a bit to be masked and inhibited from being written into a corresponding one of the memory cells, said circuit sets a corresponding one of the pairs of data buses to the floating state.
5 more elements
A semiconductor memory circuit comprising:
- a memory cell;
- a word line connected to the memory cell;
- a pair of bit lines connected to the memory cell;
- and
- a first circuit which resets the pair of bit lines to a reset potential for a second read cycle depending on data read to the pair of bit lines in a first read cycle, the first read cycle preceding the second read cycle.
2 more elements
Dependencies are inferred from the claim text.