Integrated circuit memory devices having sense amplifier driver circuits therein that improve writing efficiency

An integrated circuit memory device, comprising:

• a first memory cell containing an access transistor and a storage capacitor therein;
• a second memory cell containing an access transistor and a storage capacitor therein;
• first and second bit lines electrically connected to the access transistor in said first memory cell and the access transistor in said second memory cell, respectively;
• a sense amplifier electrically coupled to said first and second bit lines and responsive to first and second amplifier enable signals;
• and
• a driver circuit that drives the first and second amplifier enable signals to high impedance states in response to a leading edge of a write enable pulse and to active states in response to a trailing edge of the write enable pulse, said driver circuit comprising an AND logic circuit that is responsive to an inverted version of the write enable pulse, a block selection signal and a sense enable signal.