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US 6,154,403 AGranted
Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsToru Tanzawa, Tomoharu Tanaka
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprises a memory cell array with a plurality of blocks having a plurality of memory cells arranged in a matrix, a plurality of address latch circuits provided so as to correspond to the blocks, a row decoder that accesses the memory cell array in blocks according to the latched state of the plurality of address latch circuits, and a control circuit for accessing the memory cell array by latching all of the blocks to the selected state and then canceling the address latching of the selected block to the unselected state.
Claims14
A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged at intersections of a plurality of bitlines and a plurality of word lines;
- a sense amplifier and latch circuit that is selectively connected to said plurality of bitlines and senses the bitline voltage corresponding to a data in reading the data in said plurality of memory cells and outputs the voltage corresponding to the writing data onto said plurality of selected bitlines in writing the data into said plurality of memory cells;
- a precharge circuit that is selectively connected to said plurality of bitlines and outputs a voltage for preventing the change of the data in memory cells onto the bitlines unconnected to the sense amplifier and latch circuit in writing the data into a memory cell;
- and
- a control circuit for disconnecting said sense amplifier and latch circuit from all of said plurality of bitlines, connecting said precharge circuit to all of said plurality of bitlines, outputting at least one of a writing voltage and an unwriting voltage onto all of said plurality of bitlines, and simultaneously writing the data into a plurality of memory cells sharing the selected word line.
2 more elements
A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged at intersections of a plurality of bitlines and a plurality of word lines;
- a sense amplifier and latch circuit that is selectively connected to said plurality of bitlines and senses the bitline voltage corresponding to a data in reading the data in said plurality of memory cells and outputs the voltage corresponding to the writing data onto said plurality of selected bitlines in writing the data into said plurality of memory cells;
- a precharge circuit that is selectively connected to said plurality of bitlines and outputs a voltage for preventing the change of the data in memory cells onto the bitlines unconnected to the sense amplifier and latch circuit in writing the data into a memory cell;
- and
- a control circuit for disconnecting said sense amplifier and latch circuit from all of said plurality of bitlines, connecting said precharge circuit to all of said plurality of bitlines, outputting a writing voltage onto one of two adjacent bitlines and an unwriting voltage onto the other of the two adjacent bitlines, and simultaneously writing the data into a plurality of memory cells sharing the selected word line.
2 more elements
A semiconductor memory device comprising:
- memory cell array having a plurality of memory cells arranged at intersections of a plurality of bitlines and a plurality of word lines;
- a sense amplifier and latch circuit that is selectively connected to said plurality of bitlines and senses the bitline voltage corresponding to a data in reading the data in a memory cell and outputs the voltage corresponding to the writing data onto a bitline in writing the data in a memory cell;
- a precharge circuit that is selectively connected to said plurality of bitlines and outputs a voltage for preventing the change of the data in memory cells onto said plurality of bitlines unconnected to the sense amplifier and latch circuit in writing the data into a memory cell;
- and
- a control circuit for disconnecting said precharge circuit from said plurality of bitlines, connecting said sense amplifier and latch circuit to said plurality of bitlines, and simultaneously writing the same data into a plurality of memory cells sharing the selected word line.
2 more elements
A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged at intersections of a plurality of bitlines and a plurality of word lines;
- a sense amplifier and latch circuit that is selectively connected to said plurality of bitlines and senses the bitline voltage corresponding to a data in reading the data in said plurality of memory cells and outputs the voltage corresponding to the writing data onto said plurality of selected bitlines in writing the data into said plurality of memory cells;
- a precharge circuit that is selectively connected to said plurality of bitlines and outputs a voltage for preventing the change of the data in memory cells onto the bitlines unconnected to the sense amplifier and latch circuit in writing the data into a memory cell;
- and
- a control circuit for latching said sense amplifier and latch circuit so as to output a writing voltage and an unwriting voltage respectively onto said plurality of bitlines and disconnecting said sense amplifier and latch circuit from all of the bitlines.
2 more elements
Dependencies are inferred from the claim text.