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US 6,154,402 AGranted
Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorHironobu Akita
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory device, charge transfer gates and a bit line precharging/equalizing circuit are inserted in the order mentioned in a bit line pair between memory cells and a sense amplifier. When the transfer gates are off, data of the memory cells are read out to the bit line pair located on the memory cell side. Subsequently, when the transfer gates are turned on, the data are transferred to the bit line pair located on the sense amplifier side. Thereafter, the transfer gates are turned off on the basis of a threshold value of the transfer gates. Then, the memory cell data transferred to the sense amplifier side are amplified by a conventional DRAM method. The bit line precharging/equalizing circuit does not require a large area. It is therefore possible to miniaturize the semiconductor memory device.
Claims66
A semiconductor memory device comprising:
- a bit line pair including two complementary bit lines to each of which a memory cell is connected;
- a sense amplifier connected to the bit line pair, amplifying a potential difference of the bit line pair;
- charge transfer gates each inserted in and connected to a corresponding one of the two complementary bit lines of the bit line pair located between the memory cell and the sense amplifier, the charge transfer gates each having a control terminal controlling ON/OFF thereof;
- a gate potential generator connected to the charge control terminals, controlling ON/OFF of each of the charge transfer gates;
- a precharging/equalizing circuit connected to the bit line pair located on a sense amplifier side of the charge transfer gates;
- and
- a bit line potential generator connected to the precharging/equalizing circuit, generating a potential precharging and equalizing the bit line pair,
- wherein the gate potential generator controls each of the charge transfer gates such that a potential difference between the bit line pair located on a memory cell side is substantially zero just before the sense amplifier amplifies a potential difference between the bit line pair located on the memory cell side.
5 more elements
A semiconductor memory device comprising:
- a bit line pair including two complementary bit lines to each of which a memory cell is connected;
- a sense amplifier connected to the bit line pair, amplifying a potential difference of the bit line pair;
- charge transfer gates each inserted in and connected to a corresponding one of the two complementary bit lines of the bit line pair located between the memory cell and the sense amplifier, the charge transfer gates each having a control terminal controlling ON/OFF thereof;
- a gate potential generator connected to the control terminals, controlling ON/OFF off of each of the charge transfer gates;
- a precharging circuit connected to the bit line pair of a sense amplifier side of the charge transfer gates, precharging the bit line pair;
- a first signal line connected to the precharge circuit, transmitting a precharge starter signal;
- an equalizing circuit connected to the bit line pair located on the sense amplifier side of the charge transfer gates, equalizing the bit line pair;
- a second signal line connected to the equalizing circuit, transmitting an equalizing startup signal;
- and
- a bit line potential generator connected to the precharge circuit, generating a potential precharging the bit line pair,
- wherein the gate potential generator controls each of the charge transfer gates such that a potential difference between the bit line pair located on a memory cell side is substantially zero just before the sense amplifier amplifies a potential difference between the bit line pair located on the memory cell side.
8 more elements
A semiconductor memory device comprising:
- a bit line pair including two complementary bit lines to each of which a memory cell is connected;
- a sense amplifier connected to the bit line pair, amplifying a potential difference of the bit lien pair;
- charge transfer gates each inserted in and connected to a corresponding one of the two complementary bit lines of the bit line pair located between the memory cell and the sense amplifier, the charge transfer gates each having a control terminal controlling ON/OFF thereof;
- a gate potential generator connected to the charge control terminals, controlling ON/OFF of each of the charge transfer gates;
- a precharging/equalizing circuit connected to the bit line pair located on a sense amplifier side of the charge transfer gates;
- and
- a bit line potential generator connected to the precharging/equalizing circuit, generating a potential precharging and equalizing the bit line pair,
- wherein the gate potential generator generates a potential of 1/2 Vcc+Vth or more (Vcc is a power supply voltage and Vth is a threshold voltage of the charge transfer gates) during a bit line precharging/equalizing period and the bit line potential generator generates a potential of 1/2 Vcc at the same time.
5 more elements
A semiconductor memory device comprising:
- a bit line pair including two complementary bit lines to each of which a memory cell is connected;
- a sense amplifier connected to the bit line pair, amplifying a potential difference of the bit line pair;
- charge transfer gates each inserted in and connected to a corresponding one of the two complementary bit lines of the bit line pair located between the memory cell and the sense amplifier, the charge transfer gates each having a control terminal controlling ON/OFF thereof;
- a gate potential generator connected to the charge control terminals, controlling ON/OFF of each of the charge transfer gates;
- a precharging/equalizing circuit connected to the bit line pair located on a sense amplifier side of the charge transfer gates;
- and
- a bit line potential generator connected to the precharging/equalizing circuit, generating a potential precharging and equalizing the bit line pair,
- wherein the gate potential generator generates a potential of 1/2 Vcc+Vth or more (Vcc is a power supply voltage and Vth is a threshold voltage of the charge transfer gates) during a bit line precharging/equalizing period, and the bit line potential generator generates a potential of 1/2 Vcc or more after completion of equalization.
5 more elements
A semiconductor memory device comprising:
- a bit line pair including two complementary bit lines to each of which a memory cell is connected;
- a sense amplifier connected to the bit line pair, amplifying a potential difference of the bit line pair,
- charge transfer gates each inserted in and connected to a corresponding one of the two complementary bit lines of the bit line pair located between the memory cell and the sense amplifier, the charge transfer gates each having a control terminal controlling ON/OFF thereof;
- a gate potential generator connected to the charge control terminals, controlling ON/OFF of each of the charge transfer gates;
- a precharging/equalizing circuit connected to the bit line pair located on a sense amplifier side of the charge transfer gates;
- and
- a bit line potential generator connected to the precharging/equalizing circuit, generating a potential precharging and equalizing the bit line pair,
- wherein the gate potential generator supplies a potential to the control terminal of each of the charge transfer gates,
- the potential supplied to each control terminal being higher than a value in a case where each of the charge transfer gates is an n-channel MIS transistor and lower in a case where each of the charge transfer gates is a p-channel MIS transistor,
- the value being obtained by adding a threshold voltage of the charge transfer gates to a potential which is to be transferred to a corresponding one of the two complementary bit lines on the sense amplifier side, after a potential of the memory cell is output to the corresponding one of the two complementary bit lines on a memory cell side,
- so that a potential of a corresponding one of the two complementary bit lines located on the memory cell side is transferred to the sense amplifier.
8 more elements
A semiconductor memory device comprising:
- a bit line pair including two complementary bit lines to each of which a memory cell is connected;
- a sense amplifier connected to the bit line pair, amplifying a potential difference of the bit line pair;
- charge transfer gates each inserted in and connected to a corresponding one of the two complementary bit lines of the bit line pair located between the memory cell and the sense amplifier, the charge transfer gates each having a control terminal controlling ON/OFF thereof;
- a gate potential generator connected to the control terminals, controlling ON/OFF of each of the charge transfer gates;
- a precharging circuit connected to the bit line pair of a sense amplifier side of the charge transfer gates, precharging the bit line pair;
- a first signal line connected to the precharge circuit, transmitting a precharge startup signal;
- an equalizing circuit connected to the bit line pair located on the sense amplifier side of the charge transfer gates, equalizing the bit line pair;
- a second signal line connected to the equalizing circuit, transmitting an equalizing startup signal;
- and
- a bit line potential generator connected to the precharge circuit, generating a potential precharging the bit line pair,
- wherein the gate potential generator generates a potential of 1/2 Vcc+Vth or more (Vcc is a power supply voltage and Vth is a threshold voltage of each charge transfer gate) during a bit line precharging/equalizing period and the bit line potential generator generates a potential of 1/2 Vcc at the same time.
8 more elements
A semiconductor memory device comprising:
- a bit line pair including two complementary bit lines to each of which a memory cell is connected;
- a sense amplifier connected to the bit line pair, amplifying a potential difference of the bit line pair;
- charge transfer gates each inserted in and connected to a corresponding one of the two complementary bit lines of the bit line pair located between the memory cell and the sense amplifier, the charge transfer gates each having a control terminal controlling ON/OFF thereof;
- a gate potential generator connected to the control terminals, controlling ON/OFF of each of the charge transfer gates;
- a precharging circuit connected to the bit line pair of a sense amplifier side of the charge transfer gates, precharging the bit line pair;
- a first signal line connected to the precharge circuit, transmitting a precharge startup signal;
- an equalizing circuit connected to the bit line pair located on the sense amplifier side of the charge transfer gates, equalizing the bit line pair;
- a second signal line connected to the equalizing circuit, transmitting an equalizing startup signal;
- and
- a bit line potential generator connected to the precharge circuit, generating a potential precharging the bit line pair,
- wherein the gate potential generator generates a potential of 1/2 Vcc+Vth or more (Vcc is a power supply voltage and Vth is a threshold voltage of each charge transfer gate) during a bit line precharging/equalizing period, and the bit line potential generator generates a potential of 1/2 Vcc or more after completion of equalization.
8 more elements
A semiconductor memory device comprising:
- a bit line pair including two complementary bit lines to each of which a memory cell is connected;
- a sense amplifier connected to the bit line pair, amplifying a potential difference of the bit line pair;
- charge transfer gates each inserted in and connected to a corresponding one of the two complementary bit lines of the bit line pair located between the memory cell and the sense amplifier, the charge transfer gates each having a control terminal controlling ON/OFF thereof;
- a gate potential generator connected to the control terminals, controlling ON/OFF of each of the charge transfer gates;
- a precharging circuit connected to the bit line pair of a sense amplifier side of the charge transfer gates, precharging the bit line pair;
- a first signal line connected to the precharge circuit, transmitting a precharge startup signal;
- an equalizing circuit connected to the bit line pair located on the sense amplifier side of the charge transfer gates, equalizing the bit line pair;
- a second signal line connected to the equalizing circuit, transmitting an equalizing startup signal;
- and
- a bit line potential generator connected to the precharge circuit, generating a potential precharging the bit line pair,
- wherein the gate potential generator supplies a potential to the control terminal of each charge transfer gate,
- the potential being higher than a value in a case where each of the charge transfer gates is an n-channel MIS transistor but lower in a case where each of the charge transfer gates is a p-channel MIS transistor,
- the value being obtained by adding a threshold potential of the charge transfer gates to a potential which is output to a corresponding one of the two complementary bit lines and transferred to the sense amplifier side when a potential of the memory cell is output to the corresponding one of the two complementary bit lines, and
- the gate potential generator transfers a potential of a corresponding one of the two complementary bit lines located on the memory cell side, to the sense amplifier.
11 more elements
Dependencies are inferred from the claim text.