Circuit and method for memory device with defect current isolation

A method of selectively isolating a reference voltage source to an equilibration circuit from a column of a memory device, the method comprising:

• determining whether a selected column of the memory device is defective;
• when the column is defective, providing a control signal with a negative voltage to a gate of a depletion mode transistor coupled between the reference voltage source and the equilibration circuit so as to disable the depletion mode transistor;
• and
• when the column is not defective, providing a control signal with a second voltage level that varies between ground and a positive voltage so as to activate the depletion mode transistor.

A method for controlling an equilibration circuit of a memory device, the method comprising:

• determining whether a selected column of the memory device has been repaired out;
• when the selected column has been repaired out,
• reducing a column select signal to the level of the back-bias voltage, and
• providing the column select signal to a gate of a depletion mode transistor coupled between a reference voltage source and the equilibration circuit so as to isolate the equilibration voltage source from the equilibration circuit;
• and
• when the column is not defective,
• selectively varying the column select signal between ground and a positive voltage level so as to activate a depletion mode transistor, and
• providing the column select signal to the gate of the depletion mode transistor such that the equilibration voltage source selectively provides a voltage level to the equilibration circuit.

A method for isolating an equilibration source from a defective bit line, the method comprising:

• determining whether a bit line is defective by reading a fuse associated with the bit line;
• when the bit line is defective, selectively applying a back bias voltage (V.sub.BB) to a transistor to isolate the equilibration source from the defective bit line;
• and
• when the bit line is not defective, selectively applying a signal at or above ground potential to a transistor to not isolate the equilibration source from the bit line.

A column select circuit for a dynamic random access memory, the column select circuit comprising:

• a decoder circuit that determines whether a selected column address corresponds to a column that has been repaired out;
• an inverter coupled to the decoder circuit with a variable low potential;
• a pull down circuit coupled to the inverter so as to provide the low potential for the inverter;
• and
• wherein the pull down circuit provides a negative voltage to the inverter when a selected column is disabled and provides ground potential to the inverter when the selected column is operable.

A column select circuit for a dynamic random access memory, the column select circuit comprising:

• a decoder circuit, responsive to enable and column address lines, the decoder circuit determining whether a selected column address corresponds to a defective bit line;
• a plurality of column select drivers responsive to the decoder circuit, each column select driver including:
• an inverter coupled to the decoder circuit with a variable low potential, and
• a pull down circuit coupled to the inverter so as to provide the variable low potential;
• and
• wherein each pull down circuit includes:
• a first transistor with a first source/drain region coupled to ground potential and a second source/drain region coupled to the inverter,
• a second transistor with a first source/drain region coupled to a negative voltage and a second source/drain region coupled to the inverter, and
• a control circuit, responsive to an enable circuit, the control circuit coupled to a gate of the first and second transistors so as to selectively activate one of the first and second transistors.

A column select circuit for a memory device, the column select circuit comprising:

• a decoder circuit which determines whether a selected column address corresponds to a column that has been repaired out;
• and
• a plurality of column select drivers responsive to the decoder circuit, wherein each column select driver includes:
• an inverter coupled to the decoder circuit with a variable low potential;
• a pull down circuit coupled to the inverter so as to provide the variable low potential;
• and
• wherein the pull down circuit provides a negative voltage to the inverter when a selected column is disabled and provides ground potential when the selected column is operable.

A memory device comprising:

• an array of word lines and complementary bit line pairs:
• a number of memory cells which are each addressably coupled to a word line and a bit line of a complementary bit line pair;
• and
• a row decoder and a column decoder that are coupled to the array so as to select a memory cell, wherein the column decoder includes a column select circuit comprising:
• a decoder circuit which determines whether a selected column address corresponds to a column that has been repaired out;
• an inverter coupled to the decoder circuit with a variable low potential;
• and
• a pull down circuit coupled to the inverter so as to provide the variable low potential, wherein the pull down circuit provides a negative voltage to the inverter when a selected column is disabled and provides ground potential to the inverter when the selected column is operable.

A memory device comprising:

• an array of word lines and complementary bit lines;
• a number of memory cells which are each addressably coupled to a word line and a bit line of a complementary bit line pair;
• and
• a row decoder and a column decoder that are coupled to the array so as to select a memory cell, wherein the column decoder includes a column select circuit comprising:
• a decoder circuit, responsive to enable and column address lines, the decoder circuit determining whether a selected column address corresponds to a defective bit line;
• a plurality of column select drivers responsive to the decoder circuit, each column select driver including:
• an inverter coupled to the decoder circuit with a variable low potential, and
• a pull down circuit coupled to the inverter so as to provide the variable low potential;
• and
• wherein each pull down circuit includes:
• a first transistor with a first source/drain region coupled to ground potential and a second source/drain region coupled to the inverter,
• a second transistor with a first source/drain region coupled to a negative voltage and a second source/drain region coupled to the inverter, and
• a control circuit, responsive to an enable circuit, the control circuit coupled to a gate of the first and second transistors so as to selectively activate one of the first and second transistors.

A memory device comprising:

• an array of word lines and complementary bit lines;
• a number of memory cells which are each addressably coupled to a word line and a bit line of a complementary bit line pair;
• and
• a row decoder and a column decoder that are coupled to the array so as to select a memory cell, wherein the column decoder includes a column select circuit comprising:
• a decoder circuit that determines whether a selected column address corresponds to a column that has been repaired out;
• a plurality of column select drivers responsive to the decoder circuit, each column select driver including:
• an inverter coupled to the decoder circuit with a variable low potential, and
• a pull down circuit coupled to the inverter so as to provide the variable low potential;
• and
• wherein each pull down circuit includes:
• a first transistor with a first source/drain region coupled to ground potential and a second source/drain region coupled to the inverter,
• a second transistor with a first source/drain region coupled to a negative voltage and a second source/drain region coupled to the inverter, and
• a control circuit, responsive to an enable circuit, the control circuit coupled to a gate of the first and second transistors so as to selectively activate one of the first and second transistors.

A memory device comprising:

• an array of word lines and complementary bit lines;
• a number of memory cells which are each addressably coupled to a word line and a bit line of a complementary bit line pair;
• and
• a row decoder and a column decoder that are coupled to the array so as to select a memory cell, wherein the column decoder includes a column select circuit comprising:
• a decoder circuit coupled to enable and column address lines;
• and
• a plurality of column select drivers, each column select driver generating an output signal with a negative voltage when an associated bit line is determined to be defective and generating an output signal that varies between ground and a positive voltage when an associated bit line is determined to be acceptable.

A memory device comprising:

• an array of word lines and complementary bit lines;
• a number of memory cells which are each addressably coupled to a word line and a bit line of a complementary bit line pair;
• and
• a row decoder and a column decoder that are coupled to the array so as to select a memory cell, wherein the column decoder includes a column select circuit comprising:
• means for determining whether a bit line is defective;
• means, responsive to the means for determining, for selectively applying a signal with a negative voltage to a transistor to isolate the equilibration sources from the defective bit line when the bit line is defective;
• and
• means, responsive to the means for determining, for selectively applying a signal at ground potential to a transistor to not isolate the equilibration source from the bit line when the bit line is not defective.