Semiconductor storage device having redundancy circuit

A semiconductor storage device with a redundancy circuit, comprising:

• a plurality of sub-banks, each sub-bank including a plurality of input/output (I/O) units having first through mth plates, where m is an integer greater than two, each plate including a plurality of memory cells, main word lines for selecting a plurality of memory cells, sub-word lines that provide a lower level of memory cell selection than main word lines, a row redundancy circuit that includes a plurality of redundancy memory cells, redundancy main word lines, and redundancy sub-word lines;
• a plurality of redundancy main-word drivers for driving the redundancy main-word lines, each redundancy main-word driver including a main plate decoder that receives address values and activates at least one plate of an I/O unit and a redundancy main-word line within the activated plate;
• a redundancy selection control circuit that includes a redundancy plate decoder that receives address values and generates a plate select signal;
• a fuse circuit that receives the plate select signal, a pre-charge signal, and address selecting signals and generates an activating signal when the address selecting signals correspond to an address selecting value determined by programming fuse elements in the fuse circuit;
• and
• at least one sub-word selecting circuit that receives the activating signal and independently controls the activation and deactivation of redundancy sub-word selecting signals, each sub-word selecting signal controlling the activation and deactivation of a redundancy sub-word line.

A memory device, comprising:

• a plurality of memory cells;
• a plurality of main word lines;
• a plurality of sub-word lines coupled to the memory cells;
• a row redundancy circuit including
• a plurality of redundancy memory cells,
• at least one redundancy main word line,
• a plurality of redundancy sub-word lines coupled to the redundancy memory cells, and
• a plurality of redundancy sub-word drivers associated with the redundancy main word line, each redundancy sub-word driver being coupled to at least two redundancy sub-word lines and independently controlling the activation and deactivation of each of its redundancy sub-word lines according to the potential of the associated main word line and a plurality of redundancy sub-word selecting signals;
• and
• a programmable address detection circuit that includes a plurality of programmable elements that can store a plurality of programmed addresses, the programmable address detection circuit receiving a plurality of address values and generating an address match indication signal when address values match a programmed address.

A semiconductor storage device with a redundancy circuit, comprising:

• a redundancy main word line extending in a first direction and having a first point and second point apart from said first point;
• a first redundancy sub-word driver disposed adjacently to said first point and remotely from said second point and connected to said first point, for driving first and second redundancy sub-word lines that extend in said first direction, said first redundancy sub-word driver independently controlling the activation and deactivation of said first and second redundancy sub-word lines according to a first redundancy sub-word selecting signal;
• a second redundancy sub-word driver disposed adjacently to said second point and remotely from said first point and connected to said second point, for driving redundancy third and fourth sub-word lines that extend in said first direction, said second redundancy sub-word driver independently controlling the activation and deactivation of said third and fourth redundancy sub-word lines according to a second redundancy sub-word selecting signal which is different from said first redundancy sub-word selecting signal;
• and
• a redundancy selection control circuit activating one of said first and second redundancy sub-word selecting signals and deactivating the other of said first and second redundancy sub-word selecting signals.