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US 6,154,396 AGranted
Semiconductor memory device having a delay circuit set according to the storage capacity of a memory macro
AssigneeKabushiki Kaisha Toshiba
InventorsTomoaki Yabe, Shinji Miyano
Life of this patent
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Abstract
A delay circuit that delays a signal for controlling data read/write is composed of inverters, capacitors, and switches. The delay time that the delay circuit provides is set by selectively changing over the switches according to the storage capacity of a memory macro. Thus, the delay time most suitable for the storage capacity of the memory macro can be set, which allows the data read/write operation to be speeded up.
Claims40
A semiconductor memory device comprising:
- a memory macro section having at least one memory array block in which a plurality of memory cells are arranged in rows and columns;
- a data buffer block for holding input/output data;
- paired data lines connected between the memory array block and the data buffer block for transferring a signal between a selected memory cell and the data buffer block;
- a latch circuit provided in the data buffer block for latching the signal on the paired data lines;
- and
- a timing adjust circuit, coupled to the latch circuit, for adjusting the timing of activating the latch circuit according to the storage capacity of the memory macro.
3 more elements
A semiconductor memory device comprising:
- a memory macro section having at least one memory array block in which a plurality of memory cells are arranged in rows and columns;
- a data buffer block for holding input/output data;
- paired data lines connected between the memory array block and the data buffer block for transferring a signal between a selected memory cell and the data buffer block;
- a data write circuit, coupled to the paired data lines, for supplying a write signal to the paired data lines;
- and
- a timing adjust circuit, coupled to the data write circuit, for adjusting the pulse width of the write signal from the data write circuit according to the storage capacity of the memory macro.
3 more elements
A semiconductor memory device comprising:
- one or more memory array blocks in which a plurality of memory cells are arranged in rows and columns;
- a data buffer block for holding input/output data;
- paired data lines connected between the memory array block and the data buffer block for transferring a signal between a selected memory cell and the data buffer block;
- a latch circuit provided in the data buffer block for latching the signal on the paired lines;
- one or more power blocks the number of which substantially corresponding to that of the memory array blocks, the power blocks supplying power to the memory array blocks;
- and
- timing adjust circuits, coupled to the latch circuit and provided in the power blocks and interconnected for adjusting the timing of activating the latch circuit according to the number of the memory array blocks.
4 more elements
A semiconductor memory device comprising:
- at least one memory cell array block in which a plurality of memory cells are arranged in rows and columns;
- a sense amplifier block for detecting data read from the memory cells in the memory cell array block;
- a column select block placed to correspond to the sense amplifier block for making a selection from the columns;
- a row select block placed to correspond to the memory cell array block for making a selection from the rows;
- a data buffer block for holding input/output data;
- paired data lines connected between the sense amplifier block and the data buffer block for transferring a signal between a selected sense amplifier and the data buffer block;
- a latch circuit provided in the data buffer block for latching signals on the paired data lines;
- and
- timing adjust circuits, coupled to the latch circuit and provided in the column select block and the row select block and interconnected for adjusting the timing of activating the latch circuit according to the number of the memory array blocks.
6 more elements
A semiconductor memory device comprising:
- at least one memory cell array block in which a plurality of memory cells are arranged in rows and columns;
- a sense amplifier block for detecting data read from the memory cells in the memory cell array block;
- a column select block placed to correspond to the sense amplifier block for making a selection from the columns;
- a data buffer block for holding input/output data;
- paired data lines connected between the sense amplifier block and the data buffer block for transferring a signal between a selected sense amplifier and the data buffer block;
- and
- a timing adjust circuit, coupled to the data buffer block and provided to correspond to the memory array block and including a delay element that provides the same delay time as the column select circuit so that the delay of a signal passing through the delay element and the delay of a signal transferred over the paired data lines match.
4 more elements
Dependencies are inferred from the claim text.