Data input-output circuit and semiconductor data storage device provided therewith
AssigneeKabushiki Kaisha Toshipa
InventorOsamu Hirabayashi
Life of this patent
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AssigneeKabushiki Kaisha Toshipa
InventorOsamu Hirabayashi
Estimating the term…
The input-output terminal of a semiconductor memory is provided with a data input-output circuit for making it possible to improve the speed of the data input-output by synchronizing the data outputting operation and the Hi-Z control of an output buffer. The data input-output circuit comprises a temporary data storage circuit for temporarily storing data as input and outputting the data as input, an output buffer connected between the temporary data storage circuit and the input-output terminal of the semiconductor data storage device, and an output control circuit for outputting data to the temporary data storage circuit in order to control an output of the output buffer to a high impedance state when the output buffer and the input-output terminal are separated. A differential amplifier connected to the temporary data storage circuit may be provided in place of the output control circuit for performing the Hi-Z control by precharging or discharging.
A data input-output circuit of a semiconductor data storage device comprising:
A data input-output circuit of a semiconductor data storage device, comprising:
A semiconductor data storage device comprising a memory cell array in which a number of memory cells are regularly arranged in the form of a matrix, a row decoder and a column decoder for selecting the respective memory cells of a plurality of the memory cells in the memory cell array, and a data input-output circuit for inputting and outputting data of the memory cells selected by the row decoder and the column decoder, the data input-output circuit comprising:
A semiconductor data storage device comprising a memory cell array in which a number of the memory cells are regularly arranged in the form of a matrix, a row decoder and a column decoder for selecting the respective memory cells of a plurality of the memory cells in the memory cell array, and a data input-output circuit for inputting and outputting data of the memory cells selected by the row decoder and the column decoder, the data input-output circuit comprising;
Dependencies are inferred from the claim text.