US 6,154,392 A · Four-terminal EEPROM cell for storing an analog voltage and memory system using the same to store multiple bits per EEPROM cell

Abstract

A non-volatile memory based on a unique EEPROM memory. The non-volatile memory includes a plurality of data memory cells, a data programming circuit, and a first data line. Each data memory cell includes an EEPROM cell having a separate programming electrode and first and second isolation transistors. The programming electrode is coupled to the floating gate by a tunneling window. The first isolation transistor connects the EEPROM cell to the first data line. The second isolation transistor connects the programming electrode to the data programming circuit in response to a write enable signal. The data programming circuit programs a selected data memory cell by receiving a data value to be stored in that data memory cell and generating and coupling a programming signal to the second isolation transistors, the programming signal having a duration that is determined by the received data value. The memory also includes a plurality of first reference memory cells, a first reference programming circuit, and a first reference line, each first reference memory cell is structurally the same as the data memory cells. There is one first reference memory cell corresponding to each data memory cell, and that first reference cell is programmed with a predetermined value each time the corresponding data memory cell is programmed. A data memory cell is read by comparing the conductance of the first data line to the first reference line. The data reading circuit generates an output value that depends on the compared conductances. In embodiments of the invention using multiple reference cells, the various reference cells are programmed with different fixed values each time the corresponding data memory cell is programmed. The values in these reference cells are interpolated during the reading operation to determine the data value stored in the corresponding data memory cell.

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Claims12

Dependent claims

An electrically erasable, programmable memory cell formed on a semiconductor substrate, said memory cell comprising:

a source region in said substrate;
a drain region in said substrate;
a channel region connecting said source and drain regions when said channel region is conducting;
a floating gate overlying said channel region, the potential on said floating gate determining the conductivity of said channel region;
a programming electrode coupled to said floating gate by a tunneling window;
and
a programming gate overlying said floating gate, wherein said floating gate and said programming gate are capacitively coupled with a coupling capacitance of C.sub.pf and said programming electrode and said floating gate are also capacitively coupled with a coupling capacitance of C.sub.if, and wherein C.sub.pf >10 C.sub.if.

4 more elements

A non-volatile memory comprising a plurality of data memory cells, a data programming circuit, and a first data line, wherein each data memory cell comprises an EEPROM cell and first and second isolation transistors, said EEPROM cell comprising

a source region in said substrate;
a drain region in said substrate;
a channel region connecting said source and drain regions when said channel region is conducting;
a floating gate overlying said channel region, the potential on said floating gate determining the conductivity of said channel region;
a programming electrode coupled to said floating gate by a tunneling window;
and
a programming gate overlying said floating gate,
wherein said first isolation transistor connects one of said source and drain regions of said EEPROM cell to said first data line in response to a selection control signal being coupled to that isolation transistor and said second isolation transistor connects said programming electrode to said data programming circuit in response to a write enable signal being coupled to that second isolation transistor, and
wherein said data programming circuit programs a selected one of said data memory cells by receiving a data value to be stored in that data memory cell and generating and coupling a programming signal to said second isolation transistors, said programming signal having a duration determined by said received data value.

6 more elements

Dependencies are inferred from the claim text.

Description4,153 words

Summary1,445 words

#The present invention relates to EEPROM cells, and more particularly, to an EEPROM cell that can be more accurately programmed.

#EEPROM memory cells are normally used to store a single digital bit per memory cell. However, memories that store more than one bit per memory cell have been described. Such memories are often called "multilevel" memories. Multilevel memories have the potential for significantly reducing the cost per bit of storage.

#An EEPROM memory cell may be viewed as a field effect transistor with a gate that is isolated. During programming, charge is transferred to the gate by a tunneling process. The amount of charge stored on the gate determines the conductivity of the source-drain path. To store N bits per memory cell, each memory cell must provide 2.sup.N discrete distinguishable states corresponding to 2.sup.N different charge levels. The maximum number of bits that can be stored depends on the sensitivity of the circuits used to measure the conductivity and on the ability of the write circuits to precisely control the amount of charge that is transferred to the floating gate during the programming process. While sense circuits having the required precision to store and distinguish 256 are known, the precise programming of the charge still presents problems.

Brief description of the drawings5 figures

#FIG. 1 is a schematic drawing of a conventional EEPROM cell 10.

#FIG. 2 is a schematic drawing of one embodiment of an EEPROM cell 20 according to the present invention.

#FIG. 3 is a schematic drawing of the write circuitry used in one embodiment of the present invention.

Detailed description2,622 words

#The manner in which the present invention provides its advantages may be more easily understood with reference to FIG. 1 which is a schematic drawing of a conventional EEPROM cell 10. Charge is stored on a floating gate 13, which overlies the channel 9 of a field effect transistor having a source 11 and drain 12. This gate is completely surrounded by silicon dioxide. Floating gate 13 is capacitively coupled to the channel and to control gate 14 as indicated by the capacitors shown in phantom between these gates. The conductivity of the channel is controlled by the voltage on floating gate 13. This voltage, in turn, depends on the charge stored on the floating gate.

#Charge is moved between the channel and the floating gate by applying a sufficient voltage between the floating gate and the channel to cause the charge to tunnel through a tunneling window 15. To program the device, control gate 14 is held at ground and a voltage is applied to source 11. A portion of this voltage is capacitively coupled to floating gate 13. The portion of the voltage that appears on floating gate 13 depends on the relative values of C.sub.1 and C.sub.2. Since the floating gate must overlie the full width of the channel to control conductivity in the channel, C.sub.1 is roughly equal to C.sub.2 and the floating gate is elevated to a potential that is roughly half of the programming voltage.

#Prior art EEPROM cells that utilize a separate programming electrode transfer a somewhat smaller fraction of the programming voltage to the floating gate; however, the amount transferred is still too high to allow continuous programming. For example, U.S. Pat. No. 4,853,895, which is hereby incorporated by reference, teaches an EEPROM cell in which a separate programming electrode is constructed in a hole in the programming gate to solve certain leakage problems encountered when the tunneling window is too near the channel.

Facts

Application

09/417,040Filed 12 Oct 1999

Granted

28 Nov 2000

Term ended

12 Oct 2019

Estimated · how

20 years from earliest known nonprovisional domestic filing. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination. Patent term adjustment is unavailable; no adjustment was added.

Classification10 codes

G11C 11/5642
Using charge storage in a floating gate: sensing or reading circuits; Data output circuits
G11C 11/5621
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge storage in…
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 16/0416
Comprising cells containing floating gate transistors: comprising cells containing a single floating gate transistor and no select transistor,…

Four-terminal EEPROM cell for storing an analog voltage and memory system using the same to store multiple bits per EEPROM cell

Life of this patent

Four-terminal EEPROM cell for storing an analog voltage and memory system using the same to store multiple bits per EEPROM cell

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims12

Description4,153 words

Drawings

Classification10 codes

Life of this patent

Description4,153 words