Dual-stage switched-capacitor DAC with scrambled MSB's

An error-spreading digital-to-analog converter (DAC) comprising:

• a final stage including:
• an op amp for generating a final output voltage, the final output voltage being an analog equivalent to a digital input;
• a summing node connected to an input of the op amp, the summing node for charge redistribution;
• a thermometer coder, receiving most-significant-bits (MSBs) of the digital input, for generating thermometer-code signals;
• a scrambler, coupled to receive the thermometer-code signals, for re-arranging an order of the thermometer-code signals to generate scrambled MSB signals;
• MSB switches, controlled by the scrambled MSB signals, for switching between a high voltage and a low voltage;
• and
• MSB capacitors, each having a same nominal capacitance value, connected between the summing node and MSB switches;
• wherein the MSB capacitors are connected by the MSB switches to the high voltage or to the low voltage in response to the scrambled MSB signals;
• a first stage receiving least-significant-bit LSB bits of the digital input, the first stage including:
• a first-stage op amp for generating a LSB output voltage, the LSB output voltage being an analog equivalent to the LSB bits of the digital input;
• a first-stage summing node connected to an input of the first-stage op amp, the first-stage summing node for charge redistribution;
• LSB switches, coupled to receive LSB bits of the digital input without scrambling and without thermometer coding, for switching between the high voltage and the low voltage;
• and
• LSB capacitors, each having a different binary-weighted capacitance value, connected between the first-stage summing node and LSB switches;
• wherein the LSB capacitors are connected by the LSB switches to the high voltage or to the low voltage in response to the LSB bits of the digital input,
• whereby unscrambled control signals control capacitors in the first stage but scrambled control signals control capacitors in the final stage and whereby the MSBs of the digital input are thermometer coded and scrambled.

A digital-to-analog converter (DAC) comprising:

• a multi-bit digital input, the digital input having lesser-significant-bit LSB signals and most-significant-bit MSB signals;
• an analog output of an analog voltage, the analog voltage being an analog equivalent to a value of the multi-bit digital input;
• binary-weighted capacitor means for producing capacitances increasing by powers of 2;
• switch means, controlled by the LSB signals, for switching a high voltage or a low voltage to each of the binary-weighted capacitor means during a precharge phase;
• fixed-size capacitor means, for producing substantially-constant capacitances of double a capacitance of a largest of the binary-weighted capacitor means;
• second-switch means, controlled by scrambled signals, for switching the high voltage or the low voltage to each of the fixed-size capacitor means during the precharge phase;
• thermometer code means, receiving the MSB signals, for generating a thermometer code output, the thermometer code output having a number of active signals equal to a binary value of the MSB signals;
• scramble means, coupled to the thermometer code means, for generating the scrambled signals to the second switch means, the scramble means for scrambling a connection assignment of signals in the thermometer code output to the scrambled signals, wherein different signals of the thermometer code output control second switch means for different fixed-size capacitor means during different precharge phases;
• summing means, coupled to the binary-weighted capacitor means and coupled to the fixed-size capacitor means, for shifting charge during an evaluation phase after the precharge phase;
• and
• amplifier means, receiving the summing means as an input, for generating the analog output during the evaluation phase,
• whereby MSB signals are scrambled and applied to different capacitors.