Multiplier fabric for use in field programmable gate arrays

Abstract

A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of multiplier tiles. The CLEs can be operated as conventional configurable logic elements, completely disconnected from the array of multiplier tiles. However, selected CLEs can also be coupled to selected multiplier tiles, thereby creating a relatively high density multiplier circuit. Each of the multiplier tiles includes a multiplier array having a predetermined size (e.g., a 2.times.4 bit multiplier array). The multiplier tiles can be selectively coupled to one another, such that the multiplier arrays are connected to form a relatively large multiplier circuit. The desired multiplier and multiplicand bits are routed into the multiplier tiles from associated CLEs. Similarly, the resulting product bits are routed from the multiplier tiles to associated CLEs. In this manner, the FPGA is capable of implementing a relatively large multiplier circuit in an efficient manner.

Dependencies are inferred from the claim text.