Method of forming a logic array for a decoder

A method of forming a decoder logic array on a substrate, the method comprising:

• forming a first source and drain layer at a surface of the substrate;
• forming a semiconductor epitaxial layer on the first source and drain layer;
• forming a second source and drain layer at a surface of the epitaxial layer;
• etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
• forming an insulator in the first troughs;
• etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
• forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs;
• forming a conductive layer in the second troughs;
• removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer;
• forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs;
• and
• forming control line regions between opposing floating gate regions in the second troughs and separated from the floating gate regions in the second troughs by the intergate dielectric layer.

A method of forming a decoder logic array on a substrate, comprising:

• forming a first source and drain layer at a surface of the substrate;
• forming a semiconductor epitaxial layer on the first source and drain layer;
• forming a second source and drain layer at a surface of the epitaxial layer;
• etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
• forming an insulator in the first troughs;
• etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
• forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs;
• forming a conductive layer in the second troughs;
• removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer;
• forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs;
• forming split control line regions between opposing floating gate regions in the second troughs;
• separating from the floating gate regions in the second troughs by the intergate dielectric layer;
• and
• separating the split control lines by the intergate dielectric layer.