Efficient use of the base register auto-increment feature of memory access instructions
AssigneeHewlett-Packard Company
InventorVatsa Santhanam
Life of this patent
Estimating the term…
Abstract
The present invention is a compiler optimization algorithm that reduces address computation overhead for architectures that support an auto-increment addressing mode for memory access instructions. The compiler algorithm identifies opportunities for auto-increment synthesis in a low level intermediate representation. Candidate loads and stores are transformed to use a base+displacement addressing mode (even if a base+displacement addressing mode is not supported in the target architecture) prior to instruction scheduling. After instruction scheduling, the pseudo (base+displacement) instructions are transformed back into memory operations that increment their base register operands to set up effective memory addresses.
Claims23
A compiler optimization algorithm including the steps of:
- (i) identifying candidate memory access instructions for auto-increment synthesis;
- (ii) transforming candidate memory access instructions into memory access instructions that employ an addressing mode not supported by the target architecture;
- (iii) scheduling the memory access instructions that are not supported by the target architecture;
- and
- (iv) transforming the memory access instructions that are not supported by the target architecture into an auto-increment memory access instructions.
A compiler optimization algorithm for optimizing a low-level representation of a program for a target architecture that supports an auto-increment addressing mode, including the steps of:
- identifying candidate memory access instructions for auto-increment synthesis;
- transforming candidate memory access instructions into pseudo base+displacement memory access instructions, wherein the step of transforming candidate memory access instruction into pseudo base+displacement memory access instructions occurs prior to the step of instruction scheduling;
- scheduling the pseudo base+displacement memory instructions;
- and
- converting the pseudo base+displacement memory access instructions into memory access instructions that auto-increment their base register operands, wherein the step of converting the base+displacement memory access instructions into memory access instructions that auto-increment their base operands is performed after instruction scheduling.
A compiler optimization algorithm for optimizing a low-level representation of a program for a target architecture that supports an auto-increment addressing mode, including the steps of:
- identifying candidate memory access instructions for auto-increment synthesis;
- transforming candidate memory access instructions into pseudo base+displacement memory access instructions;
- and
- converting the pseudo base+displacement memory access instructions into memory access instructions that auto-increment their base resister operands, wherein the pseudo base+displacement memory access instructions are converted into memory access instructions that post-increment their base register operands, further including the step of determining whether the same base register is used by multiple memory access instruction scheduled in the same cycle.
Dependencies are inferred from the claim text.