Test method of chips in a semiconductor wafer employing a test algorithm

A method for performing a semiconductor wafer test, for testing chips in a semiconductor wafer, performed at a wafer stage;

• said wafer test being performed on a plurality of predetermined sample chips and on a plurality of judgment subject chips both of which are located in a test effective region on a wafer;
• said sample chips being subjected to a sample test respectively;
• said judgment subject chips being subjected to a good/defective judgment test based on a test algorithm after said sample test of said sample chips;
• wherein said test algorithm comprises:
• (a) a chip layout rule for determining the layout of said sample chips and said judgment subject chips so that said judgment subject chips are adjoined or surrounded by said sample chips by assigning respective chip address to each chip that indicate the location on said wafer, and by determining the chip layout based on statistical data of a defect generation distribution including address information of defective chips that have occurred in said test effective region;
• (b) a sample test rule for determining a procedure of said sample test to be performed on said sample chips;
• and
• (c) a good-defective judgment rule, for judging said judgment subject chips, determined based on good/defective judgment prediction that are statistically deducted both from the statistical data and good/defective test results of said sample chips.