Method of evaluating fault coverage

A method of evaluating fault coverage of a test pattern, which is applicable to first and second circuits, the first and second circuits respectively including a common logic circuit, and fault coverage of the test pattern being coverage of faults present in the common logic circuit, the method comprising the steps of:

• preparing a fault list in which faults are assumed by sampling in a logic circuit;
• performing fault simulation for the first circuit by inputting a predetermined test pattern used for testing the common logic circuit into the first circuit;
• performing fault simulation for the second circuit by inputting the predetermined test pattern which is modified to be applicable to the logic circuit included in the second circuit;
• preparing first and second fault information lists by adding to the fault list informations on detection of the assumed faults, which are obtained by the fault simulations for the first and second circuits, respectively;
• and
• comparing the first and second fault information lists to evaluate whether or not the faults assumed to occur in the common logic circuits included in the first and second circuits respectively are detected with use of the predetermined test pattern.

A method of evaluating fault coverage of first and second test patterns used for testing first and second circuits, the first circuit including a first logic circuit, and the second circuit including a second logic circuit slightly different from the first logic circuit, and the fault coverages of the first and second test patterns used for testing the first and second circuits are coverages of faults which occur in the first and second logic circuits, the method comprising:

• a first step of
• preparing a first fault list in which faults are assumed by sampling in the first logic circuit,
• performing fault simulation for the first circuit by inputting the first test pattern into the first circuit,
• preparing a first fault information list by adding to the first fault list information on detection of the assumed faults, which is obtained by the fault simulation for the first circuit,
• preparing a second fault list by extracting from the first fault list faults, which are assumed to occur in the first logic circuit and not assumed to occur in the second logic circuit, with use of a difference extraction program,
• preparing a third fault list marking that the faults corresponding to the second fault list can be deleted from the first fault list, otherwise, ignored, with use of a program for marking the faults corresponding to the second fault list can be deleted from the first fault list, otherwise, ignored,
• performing a fault simulation for the second logic circuit by inputting the second test pattern into the second logic circuit in which the faults in the third fault list are assumed to occur,
• preparing a third fault information list relating to a common portion of the first and second logic circuits by adding to the third fault list information on detection of the assumed faults, which is obtained by the fault simulation for the second logic circuit,
• preparing a second fault information list marking that the faults included in the second fault list can be deleted from the first fault list, otherwise, ignored in the first fault list, with use of a program for marking the faults included in the second fault list can be deleted from the first fault list, otherwise, ignored the first fault list, and
• comparing the second and third fault information lists in order to evaluate whether or not the faults assumed to occur in the common portion of the first and second logic circuits are detected;
• and
• a second step of
• preparing a fourth fault list by extracting a circuit portion included in the second logic circuit and not included in the first logic circuit with use of the difference extraction program, and assuming that faults occur in the entire extracted circuit portion,
• performing a fault simulation for the second logic circuit by inputting the second test pattern into the second logic circuit in which the faults in the fourth fault list are assumed to occur,
• preparing a fourth fault information list relating to a portion not included in the first logic circuit and added to the second logic circuit by adding to the fourth fault list information on detection of the assumed faults, which is obtained from the fault simulation for the second circuit, and
• comparing the fault coverage obtained from the fourth fault information list and a fault coverage standard to evaluate fault coverage of the second test pattern for the added portion not included in the first logic circuit and added to the second logic circuit.