Integrated circuit having memory built-in self test (BIST) for different memory sizes and method of operation

An application specific integrated circuit comprising:

• a standard central processing unit module;
• a memory module connected to the central processing unit module and having a selected size selected from a set of alternative memory sizes
• the standard central processing unit module including a memory interface device having an interface output connected to the memory module;
• the standard central processing unit module including a memory test device connected to the memory module;
• the memory test device including a size selector input, such that the memory test device is operable to test a memory module of any of the alternative memory sizes in response to alternative memory size codes received on the size selector input;
• and
• a switch having a first input, a second input, and an output, and operable to select exactly one of the inputs for connection to the output;
• and
• the output of the switch being connected to the memory input node, the first input of the switch being connected to the memory test device, and the second input of the switch being connected to the memory interface device.

An electronic circuit comprising:

• a processor including a memory device having a memory input node
• the memory device having a memory size selected from a group of selected memory sizes;
• a memory interface device having an interface output connected to the memory input node;
• a memory test device connected to the memory input node;
• the memory test device including a plurality of selectable parameter sets, each parameter set corresponding to a different memory size selected from the group of selected memory sizes;
• and
• the memory test device having a memory size selector input that is hard wired to continuously generate a code corresponding to the parameter set corresponding to the memory size of the memory device.

An application specific integrated circuit comprising:

• a standard central processing unit module;
• a memory module connected to the central processing unit module and having a selected size selected from a set of alternative memory sizes;
• the standard central processing unit module including a memory interface device having an interface output connected to the memory module;
• the standard central processing unit module including a memory test device connected to the memory module;
• and
• the memory test device including a size selector input hard wired to a code corresponding to the memory module, such that the memory test device is operable to test the memory module.