US 6,151,682 A · Digital signal processing circuitry having integrated timing information

Abstract

Digital signal processing circuitry implemented in ASICs or FPGAs is built by combining multi-component constructs (e.g. macrocells). These circuits may be modified to include a timing channel by augmenting selected ones of the constructs to include a path which propagates a timing signal with a delay that compensates for the signal processing delay through the construct. The selected constructs are those that are used in a critical processing path in the digital signal processing circuitry. A timing compensation circuit may also be defined as a construct. This block receives two digital data signals having accompanying timing signals and delays the first signal that provides valid data until the second signal also provides valid data, as determined by their timing signals. A configurable arithmetic and logic unit (ALU) made using these techniques includes a timing compensation circuit, a look-up table and an accumulator. The configurable ALU may also include a timing signal selection circuit which selects between the each of two input timing signals, the logical AND of the input timing signals and the logical OR of the two input timing signals to produce an output timing signal. A programmable multiply-accumulator includes a matrix of multipliers, each of which may receive one of a plurality of input signals. The input signals are delayed through a pipeline and a portion of this pipeline is reserved for delaying one or more timing signals associated with the plurality of input signals. The delayed timing signals form the timing signals that are associated with the output signal of the programmable multiply accumulator.

Claims9

Dependent claims

A method of implementing digital signal processing circuitry including the steps of:

identifying a plurality of multi-component constructs to be used to process the digital signals, each of the plurality of multi-component constructs having a processing delay;
modifying a plurality of the identified constructs to include a channel for conveying a timing signal to define a plurality of auxiliary multi-component constructs, wherein the timing channel of each of auxiliary multi-component constructs delays the timing signal by an amount of time substantially equal to the processing delay of the corresponding multi-component construct;
wherein, ones of the identified multi-component constructs, that do not change values of the processed digital signals, modify the multi-component constructs by adding a path through the respective multi-component constructs that processes the timing signal in parallel with the digital signal that is being processed;
defining the digital signal processing circuitry using the plurality of multi-component constructs;
and
replacing selected ones of the assembled multi-component constructs with corresponding ones of the auxiliary multi-component constructs to define circuitry which propagates a timing signal through the digital signal processing circuitry.

3 more elements

A configurable arithmetic and logic unit comprising:

first and second input ports for receiving first and second digital data signals, each of the first and second digital data signals including a data portion and a timing portion;
a data alignment circuit responsive to the timing portions of the first and second digital data signals and to a timing control signal for aligning the first and second digital data signals;
a look up table responsive to a programming control signal and to the data portion of at least one of the first and second digital data signals as an address value for producing an output data signal determined by the programming control signal,
a timing path, coupled in parallel with the look-up table, for delaying the timing portion of the digital data signals to match a processing delay through the look-up table;
and
a control port for receiving the timing control signal and the program control signal from an external controller.

3 more elements

Dependencies are inferred from the claim text.

Digital signal processing circuitry having integrated timing information

Life of this patent

Digital signal processing circuitry having integrated timing information

Life of this patent

Abstract

Claims9