US 6,151,681 A · Dynamic device power management

Abstract

A power management method and system which includes providing a system having a plurality of clock operated circuits, each clock operated circuit being operable in response to the receipt of clock signals. A first subplurality of the clock operated circuits receives an uninterrupted stream of clock signals and thereby is uninterruptably operable and a second plurality of the clock operated circuits receives a normally off interruptable stream of clock signals and is normally inoperable. The system is sampled for the presence of data signals being input thereto. The clock signals are sent to the second plurality of circuits in response to the sampling the presence of data signals being input to the system to cause the second plurality of circuits to be operable. The data signals are transmitted to the second plurality of circuits after a time delay equal to or greater than the expired time from the sampling to the sending. The system can have a plurality of input/output terminals with the sampling comprising being at each of the input/output terminals. The system includes a clock for providing the clock signals and a decode logic for sampling at one of the input/output terminals and an arbiter circuit for sampling at the other input/output terminal.

Claims16

Dependent claims

A power management method which comprises the steps of:

(a) providing a system having a plurality of clock operated circuits, each of said clock operated circuits being operable in response to the receipt of clock signals, with a first subplurality of said clock operated circuits receiving an uninterrupted stream of clock signals from a first clock and thereby being uninterruptably operable and a second subplurality of said clock operated circuits receiving a normally off interruptible stream of clock signals from a second clock and being normally inoperable, wherein the first and second clocks are continuously synchronized in phase and have a common operating frequency;
(b) sampling said system for the presence of data signals being input to said system;
(c) sending said clock signals from said second clock to said second subplurality of circuits in response to the sampling the presence of data signals being input to said system to cause said second subplurality of circuits to be operable;
and
(d) transmitting said data signals to said second subplurality of circuits after a time delay equal to or greater than the expired time from said step of sampling to said step of sending.

2 more elements

A power management system which comprises:

(a) a system having a plurality of clock operated circuits, each of said clock operated circuits being operable in response to the receipt of clock signals, with a first subplurality of said clock operated circuits receiving an uninterrupted stream of clock signals from a first clock and thereby being uninterruptably operable and a second subplurality of said clock operated circuits receiving a normally off interruptible stream of clock signals from a second clock and being normally inoperable, wherein the first and second clocks are continuously synchronized in phase and have a common operating frequency;
(b) sampling circuitry for sampling said system for the presence of data signals being input to said system;
and
(c) circuitry sending clock signals from said second clock to said second subplurality of circuits in response to the sampling the presence of data signals being input to said system to cause said second subplurality of circuits to be operable;
(d) said system including a time delay for transmitting said data signals to said second subplurality of circuits after said time delay equal to or greater than the expired time from said sampling to said sending.

2 more elements

Dependencies are inferred from the claim text.

Dynamic device power management

Life of this patent

Dynamic device power management

Life of this patent

Abstract

Claims16