Anti-theft mechanism for mobile computers
AssigneeIntel Corporation
InventorDerek L. Davis
Life of this patent
Estimating the term…
Abstract
An electronic system that remains disabled after power-on until its user is recognized. The electronic system includes a host processor and a deactivation circuit coupled to the host processor. The deactivation circuit places the host processor into an inoperative state until the user is recognized. In one embodiment, the deactivation circuit is a security processor coupled to a reset input of the host processor. The security processor includes a processing unit and an internal memory unit to contain software required by the host processor to complete a booting procedure.
Claims17
An electronic system comprising:
- a host processor;
- a power-on reset circuit;
- and
- a deactivation circuit coupled to the host processor and the power-on reset circuit, the deactivation circuit to prevent the host processor from receiving instructions by continuously outputting an active reset signal to the host processor in response to a system power-on signal by the power-on reset circuit, the active reset signal places the host processor in an inoperative state until a user of the electronic system is recognized upon which the reset signal is deactivated.
An electronic system comprising:
- power means for transmitting a power-on reset signal at power-up of the electronic system;
- processor means for executing a plurality of instructions;
- and
- deactivation means for preventing the processor means from obtaining a plurality of boot instructions in response to receipt of the system power-on reset signal from the power means and for continuously providing an active reset signal that places the processor means in an inoperative state immediately after power-up of the electronic system until a user of the electronic system is recognized, the deactivation means being coupled to the processor means and the power means.
An electronic system comprising:
- a host processor;
- and
- a deactivation circuit coupled to the host processor, the deactivation circuit to (1) place the host processor in an inoperative state immediately after a system power-on reset signal is initiated in order to prevent the host processor from receiving any basic input output system (BIOS) instructions until a user of the electronic system is recognized by comparing the input data with data preloaded for use in identifying one or more authorized users, and (2) store BIOS instructions fetched by the host processor after the user is recognized.
A method for ensuring security of an electronic system, the method comprising:
- placing a host processor in an inoperative state after power-on, which prevents the host processor from fetching any basic input output system (BIOS) instructions, by configuring a deactivation circuit to continuously output an active RESET signal to the host processor;
- determining whether an intended user of the electronic system is recognized as an authorized user of the electronic system;
- continuing to maintain the host processor in the inoperative state until the user is recognized as the authorized user;
- and
- placing the host processor in an operative state when the user is recognized as the authorized user.
Dependencies are inferred from the claim text.