Methods and apparatus for reducing interference in a branch history table of a microprocessor

A method of predicting outcomes of a plurality of branch instructions executed in a microprocessor, comprising:

• a) maintaining a branch history table comprising a plurality of entries;
• b) maintaining static prediction information for a plurality of branch instructions;
• c) predicting outcomes of the plurality of branch instructions, each outcome being predicted at least partly in response to:
• i) the static prediction information;
• and
• ii) an entry in the branch history table;
• and
• d) after executing each of the plurality of branch instructions, updating an entry in the branch history table at least partly in response to the exclusive OR of:
• i static prediction information corresponding to a given one of the plurality of branch instructions;
• and
• ii an indication as to whether execution of the given one of the plurality of branch instructions resulted in a branch being taken or not taken.

A method of reducing interference in a branch history table of a microprocessor, comprising:

• a) predicting outcomes of a plurality of branch instructions in a computer program at least partly in response to the exclusive OR of:
• i a hint encoded in a given branch instruction;
• and
• ii an entry in a branch history table;
• and
• b) after execution of the given branch instruction, updating an entry in the branch history table at least partly in response to whether the hint encoded in the given branch instruction was correct.

A method of reducing interference in a branch history table of a microprocessor, comprising:

• a) predicting outcomes of a plurality of branch instructions in a computer program, at least partly in response to:
• i) hints encoded in the branch instructions;
• and
• ii) entries in a branch history table;
• and
• b) after execution of a given branch instruction, updating an entry in the branch history table at least partly in response to the exclusive OR of:
• i a hint encoded in the given branch instruction;
• and
• ii an indication as to whether execution of the given branch instruction resulted in a branch being taken or not taken.

Apparatus in a microprocessor for predicting whether branches identified in a plurality of branch instructions will be taken or not taken, comprising:

• a) a branch history table comprising a plurality of entries;
• b) one or more data storage locations for storing static prediction information corresponding to a plurality of branch instructions;
• c) a first logic gate, comprising:
• i) an input for receiving static prediction information derived from an addressed one of the one or more data storage locations;
• ii) an input for receiving information derived from at least one entry in the branch history table;
• and
• iii) a branch prediction output which is indicative of whether one of the plurality of branch instructions will be taken or not taken;
• d) a second logic gate, comprising:
• i) an input for receiving static prediction information derived from an addressed one of the one or more data storage locations;
• ii) an input for receiving information which is indicative of whether a branch identified in a branch instruction was taken or not taken;
• and
• iii) a branch history update output which is indicative of whether the static prediction information corresponding to a branch instruction was correct;
• wherein the branch history update output is received by the branch history table.