System and method of maintaining and utilizing multiple return stack buffers

An instruction pipeline in a microprocessor, comprising:

• an instruction fetch unit for fetching a plurality of macro-code instructions from a memory device, each of the plurality of macro-code instructions corresponding to at least one micro-code instruction, the instruction fetch unit capable of recognizing a subroutine CALL macro-code instruction, the instruction fetch unit determining a respective first return address for each subroutine CALL macro-code instruction recognized by the instruction fetch unit, the instruction fetch unit further capable of recognizing a RETURN FROM SUBROUTINE macro-code instruction;
• a first return address stack, coupled to the instruction fetch unit, the instruction fetch unit pushing each respective first return address onto the first return address stack, wherein the instruction fetch unit pops one respective first return address from the first return address stack for each RETURN FROM SUBROUTINE macro-code instruction the instruction fetch unit recognizes;
• a decode unit for decoding the each of the plurality of macro-code instructions into the at least one corresponding micro-code instruction, the decode unit capable of recognizing a subroutine CALL macro-code instruction, the decode unit determining a respective second return address for each subroutine CALL macro-code instruction recognized by the decode unit, the decode unit further capable of recognizing a RETURN FROM SUBROUTINE macro-code instruction;
• a second return address stack, coupled to the decode unit, the decode unit pushing each respective second return address onto the second return address stack, and wherein the decode unit pops one respective second return address from the second return address stack for each RETURN FROM SUBROUTINE macro-code instruction the decode unit recognizes;
• a third unit for executing each of the plurality of micro-code instructions;
• a fourth unit for retiring each macro-code instruction corresponding to the executed plurality of micro-code instructions, the fourth unit capable of recognizing a subroutine CALL macro-code instruction, the fourth unit determining a respective third return address for each CALL macro-code instruction recognized by the fourth unit, the fourth unit further capable of recognizing a RETURN FROM SUBROUTINE macro-code instruction;
• and
• a third return address stack, coupled to the fourth unit, the fourth unit pushing each third respective third return address onto the third return address stack, and wherein the fourth unit pops one respective third return address from the third return address stack for each RETURN FROM SUBROUTINE macro-code instruction the fourth unit recognizes.