Methods and apparatus for efficient control of floating-point status register

Apparatus for controlling floating-point calculations comprising:

• a computer comprising a floating-point computation unit, floating-point registers and a floating-point status register having two or more status fields, each containing flag information and control information;
• means for executing a sequence of floating-point instructions in said floating-point computation unit in accordance with the control information obtained from said floating-point status register;
• and
• means for updating the control information in a selected status field of said floating-point status register in response to a floating-point instruction.

A method for controlling floating-point calculations in a computer comprising a floating-point computation unit, floating-point registers and a floating-point status register, comprising the steps of:

• providing in said floating-point status register two or more status fields, each containing flag information and control information;
• executing a sequence of floating-point instructions in said floating-point computation unit;
• setting a flag bit in a selected status field of said floating-point status register in response to an exception that occurs during execution of said sequence of floating-point instructions;
• and
• clearing the flag bit in the selected status field of said floating-point status register in response to a floating-point instruction subsequent to said sequence of floating-point instructions.

A method for controlling floating-point calculations in a computer comprising a pipelined floating-point computation unit, floating-point registers, and a floating-point status register, comprising the steps of:

• providing control information for controlling operations of said pipelined floating-point computation unit;
• updating said control information to provide different versions of said control information without flushing said pipelined floating-point computation unit;
• associating the different versions of said control information with different operations of said pipelined floating-point computation unit;
• and
• controlling operations of said floating-point computation unit in response to the associated version of said control information.

Apparatus for controlling floating-point calculations comprising:

• a computer comprising a floating-point computation unit, floating-point registers and a floating-point status register having two or more status fields, each containing flag information and control information;
• means for executing a sequence of floating-point instructions in said floating-point computation unit;
• means for setting a flag bit in a selected status field of said floating-point status register in response to an exception that occurs during execution of said sequence of floating-point instructions;
• and
• means for clearing the flag bit in the selected status field of said floating-point status register in response to a floating-point instruction subsequent to said sequence of floating-point instructions.

Apparatus for controlling floating-point calculations comprising:

• a computer comprising a pipelined floating-point computation unit, floating-point registers, and a floating-point status register;
• means for providing control information for controlling operations of said pipelined floating-point computation unit;
• means for updating said control information to provide different versions of said control information without flushing said pipelined floating-point computation unit;
• means for associating the different versions of said control information with different operations of said pipelined floating-point computation unit;
• and
• means for controlling operations of said floating-point computation unit in response to the associated version of said control information.