Communication link with isochronous and asynchronous priority modes coupling bridge circuits in a computer system
AssigneeAdvanced Micro Devices, Inc.
InventorsLarry Hewitt, Dale E. Gulick
Life of this patent
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Abstract
A computer system includes a first processor integrated circuit. A first bridge integrated circuit is coupled to the processor via a host bus. The computer system includes an interconnection bus that couples the first bridge circuit to a second bridge circuit. The interconnection bus provides a first transfer mode for asynchronous data and a second transfer mode for isochronous data. The interconnection bus provides for a maximum latency and a guaranteed throughput for asynchronous and isochronous data.
Claims24
A computer system comprising:
- a processor integrated circuit including a central processing unit;
- a first integrated circuit coupled by a host bus to the processor integrated circuit;
- a second integrated circuit;
- and
- an interconnection bus coupling the first and second integrated circuits, the interconnection bus transferring data in frames, the interconnection bus coupled to transfer data in asynchronous priority mode during a first part of each frame, in which asynchronous traffic is transferred instead of isochronous traffic if there are any asynchronous requesters for the interconnection bus and to transfer data in isochronous priority mode during other parts of at least some frames.
A method of communicating information in a computer system that includes a processor coupled to a first bridge integrated circuit by a host bus and an interconnection bus connecting a second bridge integrated circuit to the first bridge integrated circuit, the method comprising:
- transferring information between the first and second bridge integrated circuits in asynchronous priority mode in which asynchronous information is transferred instead of isochronous information if there are any asynchronous requesters, during a first part of each frame;
- selectably transferring information between the first and second bridge integrated circuits in isochronous priority mode, in which transfer of isochronous information is given priority over transfers of asynchronous information.
An integrated circuit comprising:
- a plurality of input and output terminals for connecting to an interconnection bus;
- an interface coupled to the input and output terminals, the interface coupled to send and receive data in frames, the interface responsive to transfer information in asynchronous priority mode during a first part of a frame and in isochronous priority mode during other parts of the frame, the interconnect bus selectably switching to isochronous priority mode during the frame according to an amount of isochronous traffic transferred during the frame.
Dependencies are inferred from the claim text.