Method and circuit for detecting overflow in operand multiplication

Abstract

Disclosed is a method and circuit for detecting overflow when multiplying operands. The disclosed method and circuit is configured to operate in parallel with a multiplier configured to multiply first and second n bit operands. In general, the multiplier circuit generates result operand which represents a multiplication of the first and second n bit operands. An overflow detection circuit is coupled to the multiplier circuit and configured to generate an overflow signal which indicates that the multiplication of the first and second n bit operands results in an overflow condition. The multiplier circuit comprises a compression circuit configured to generate the first and second 2n bit partial product operands as a function of the first and second n bit operands. An addition of the first and second 2n bit partial product operands produces the result operand. The multiplier circuit also includes a carry generation circuit configured to generate at least one carry bit representing a carry value of adding the (n-1) least significant bits of the first and second 2n bit partial product operands. The carry bit along with the most significant (n+1) bits of the first and second 2n bit partial product operands are provided to the overflow detection circuit. In response, the overflow detection circuit is configured to generate the overflow signal as a function of the carry bit and the most significant (n+1) bits of the first and second 2n bit partial product operands.

Dependencies are inferred from the claim text.