Method and apparatus for formatting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations
AssigneeIntrinsity, Inc.
InventorsJeffrey S. Brooks, James S. Blomgren
Life of this patent
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Abstract
The present invention describes an apparatus and method that formats the output fraction result of an ANSI/IEEE 754-1985 floating point arithmetic operation where parallel normalization and rounding of the intermediate fraction result has occurred. The output fraction is formatted using all or some of the bits from the output of either the rounder circuit or the normalizer circuit.
Claims20
A format control circuit that formats the result mantissa of an ANSI/IEEE 754-1985 floating point arithmetic operation, comprising:
- an input from the rounder circuit;
- an input from the normalizer circuit;
- an input from the select control circuit;
- and
- a multiplexer that couples to said input from the select control circuit, said input from the normalizer circuit, and said input from the rounder circuit, said multiplexer generates a result mantissa for a floating point arithmetic operation using a formatting procedure selected from the following group:
- D1, D3, D4, and D5.
A system that formats the result mantissa of an ANSI/IEEE 754-1985 floating point arithmetic operation, comprising:
- an input from the rounder circuit;
- an input from the normalizer circuit;
- an input from the select control circuit;
- and
- a multiplexer that couples to said input from the select control circuit, said input from the normalizer circuit, and said input from the rounder circuit, said multiplexer generates a result mantissa for a floating point arithmetic operation using a formatting procedure selected from the following group:
- D1, D3, D4, and D5.
A method that formats the result mantissa of an ANSI/IEEE 754-1985 floating point arithmetic operation, comprising:
- receiving an input from the rounder circuit;
- receiving an input from the normalizer circuit;
- receiving an input from the select control circuit;
- and
- generating a result mantissa for a floating point arithmetic operation using a formatting procedure selected from the following group:
- D1, D3, D4, and D5 wherein each said formatting procedure uses said input from the select control circuit and one or more of the following inputs:
- said input from the rounder circuit, and said input from the normalizer circuit.
A method to manufacture a format control circuit that formats the result mantissa of an ANSI/IEEE 754-1985 floating point arithmetic operation, comprising:
- providing an input from the rounder circuit;
- providing an input from the normalizer circuit;
- providing an input from the select control circuit;
- and
- coupling a multiplexer to said input from the rounder circuit, to said input from the normalizer circuit, and to said input from the select control circuit, said multiplexer generates a result mantissa for a floating point arithmetic operation using a formatting procedure selected from the following group:
- D1, D3, D4, and D5.
Dependencies are inferred from the claim text.