Digital demodulator
AssigneeHyundai Electronics Ind. Co., Ltd.
InventorKwang-Woo Lim
Life of this patent
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Abstract
A digital demodulator includes: a local oscillator for generating a predetermined frequency signal; a mixer for mixing an intermediate frequency (IF) signal with a local oscillation frequency signal output by the local oscillator; an A/D converter for converting a signal output by the mixer into a digital signal; an I and Q signal generator for producing I and Q signals from an output of the A/D converter; and a compensation unit for compensating the signals I and Q for phase errors.
Claims10
A digital demodulator comprising local oscillation means, mixing means, A/D conversion means, hilbert transform means, delay means, multiplication means, filter means, frequency error detect means, a loop filter and numerically controlled oscillation means:
- wherein the hilbert transform means comprises:
- a first shift register for sequentially shifting a received signal to multiple shift registers;
- a second shift register for sequentially shifting a last delay output of the first shift register to multiple shift registers;
- a first adding unit having a number of adders for selectively adding signals output by the first and second shift registers;
- a multiplication unit having a number of multipliers for respectively multiplying the signals output from the adders in the first adding unit by predetermined tap coefficients;
- and
- a second adding unit having a number of adders for performing selective adding of each signal output from the number of multipliers in the multiplication unit, and
- wherein the frequency error detect means comprises:
- a first delay circuit for delaying the signal I from the filter means;
- a second delay circuit for delaying the signal Q from the filter means;
- a first exclusive OR circuit for performing an exclusive OR operation with respect to the output of the delay circuit and the signal Q;
- a second exclusive OR circuit for performing the exclusive OR operation with respect to the output of the delay circuit and the signal I;
- and
- an adder for summing up the outputs of the two exclusive OR circuits.
Dependencies are inferred from the claim text.