Multiport data switch having data frame VLAN tagging and VLAN stripping

A method for administering data packet communication in an integrated multiport network switch having a plurality of ports for transmitting data packets to and receiving data packets from a data network, each port having associated therewith a media access controller (MAC), at least one of said ports being designated a VLAN port for virtual local area network (VLAN) operation, said method comprising the steps of:

• determining whether a data packet received at a designated VLAN port is a VLAN tagged packet;
• stripping the VLAN tag from said packet in response to a positive VLAN tagged packet determination in said determining step;
• forwarding the stripped VLAN tag to a rules checker in the switch;
• separately storing the VLAN tag data and the remainder of the stripped packet data in untagged format in a memory external to said chip;
• determining whether said packet is to be transmitted as a VLAN packet at a designated VLAN port;
• in response to a positive VLAN transmission determination, combining said VLAN tag data and remainder data to obtain a packet in VLAN tagged format;
• wherein said combining step comprises the steps of:
• dequeuing said VLAN tag data;
• multiplexing said VLAN tag data with packet data from said external memory;
• and
• writing the multiplexed data to a memory in a transmit FIFO at the MAC at the VLAN port designated for transmission.

In an integrated multiport network switch comprising an integrated chip having a plurality of ports for transmitting data packets to and receiving data packets from a data network, each port having associated therewith a media access controller (MAC), at least one of said ports being designated a VLAN port for virtual local area network (VLAN) operation, a method for processing a packet to be transmitted to one or more VLAN destinations from a designated VLAN port, comprising the steps of:

• dequeuing VLAN tag data related to said packet;
• multiplexing said VLAN tag data with packet data obtained from a memory external to said chip;
• and
• writing the multiplexed data to a memory in a transmit FIFO at the MAC at the VLAN port designated for transmission;
• wherein the memory in said transmit FIFO is a single port random access memory (RAM) that alternately transfers between read and write operation states in successive clock cycles, and said writing step comprises the steps of:
• feeding packet data to the transmit FIFO in successive clock cycles;
• buffering data received by said FIFO during clock cycles in which said single port RAM is in a read operation state;
• and
• applying said buffered data and data received by said FIFO to said single port RAM during clock cycles in which said single port RAM is in a write operation state.